From patchwork Tue Jul 7 19:17:09 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adrian Alonso X-Patchwork-Id: 492578 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id BC56C140788 for ; Wed, 8 Jul 2015 05:18:10 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932198AbbGGTSJ (ORCPT ); Tue, 7 Jul 2015 15:18:09 -0400 Received: from mail-bl2on0106.outbound.protection.outlook.com ([65.55.169.106]:13939 "EHLO na01-bl2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932627AbbGGTSF (ORCPT ); Tue, 7 Jul 2015 15:18:05 -0400 Received: from CY1PR0301MB1225.namprd03.prod.outlook.com (10.161.212.147) by CY1PR0301MB0700.namprd03.prod.outlook.com (10.160.159.142) with Microsoft SMTP Server (TLS) id 15.1.201.16; Tue, 7 Jul 2015 19:18:03 +0000 Received: from DM2PR03CA0002.namprd03.prod.outlook.com (10.141.96.12) by CY1PR0301MB1225.namprd03.prod.outlook.com (10.161.212.147) with Microsoft SMTP Server (TLS) id 15.1.207.19; Tue, 7 Jul 2015 19:18:02 +0000 Received: from BL2FFO11FD018.protection.gbl (2a01:111:f400:7c09::145) by DM2PR03CA0002.outlook.office365.com (2a01:111:e400:2428::12) with Microsoft SMTP Server (TLS) id 15.1.213.14 via Frontend Transport; Tue, 7 Jul 2015 19:18:01 +0000 Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=freescale.com; freescale.mail.onmicrosoft.com; dkim=none (message not signed) header.d=none; Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Received: from az84smr01.freescale.net (192.88.158.2) by BL2FFO11FD018.mail.protection.outlook.com (10.173.161.36) with Microsoft SMTP Server (TLS) id 15.1.201.10 via Frontend Transport; Tue, 7 Jul 2015 19:18:01 +0000 Received: from bluefly.am.freescale.net (bluefly.am.freescale.net [10.81.17.130]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id t67JHwGW023526; Tue, 7 Jul 2015 12:17:59 -0700 From: Adrian Alonso To: , , , , CC: , , , , , , Subject: [PATCH 3/4][v3] ARM: imx: pinctrl-imx: imx7d: add support for iomuxc lpsr Date: Tue, 7 Jul 2015 14:17:09 -0500 Message-ID: <1436296630-20296-3-git-send-email-aalonso@freescale.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1436296630-20296-1-git-send-email-aalonso@freescale.com> References: <1436296630-20296-1-git-send-email-aalonso@freescale.com> X-EOPAttributedMessage: 0 X-Microsoft-Exchange-Diagnostics: 1; BL2FFO11FD018; 1:OLe42+hEt+dRzqYRi9YZw80tonjuQ9XMrKX6n/0O/MPHkzYM8POn0jD8bFhKMwHAQVcogX/anmf+CLZPPpIecHC3e/HfBDSA9v5CGeICRAzeFBz/bw5bxIsn5kESUceOFIIoQ3YC+RwmGCjTKFVTHhE8JgT/MdbxmCX1XV19QjVIBuecXygxrndDlui4Lr2JtkYZ93bB5PjpOmBBIPRljs1mXykgyvkzipHvaAR86wmgDSvcQ5XVzMfhqjP16FMEup1zAq6NTMjLyWo/PqGaK411eGf/qD36JwHbgrV4zzBlmfLx5t18epwPrFVmn72PLVWx6tKrXqQs74nj0rl08A== X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019020)(6009001)(2980300002)(339900001)(189002)(199003)(46102003)(106466001)(6806004)(48376002)(85426001)(2201001)(76176999)(92566002)(5003940100001)(50226001)(50986999)(105606002)(189998001)(229853001)(77096005)(575784001)(86362001)(5001770100001)(2950100001)(19580395003)(33646002)(50466002)(47776003)(107886002)(19580405001)(62966003)(104016003)(77156002)(87936001)(5001960100002)(36756003)(2101003)(4001430100001); DIR:OUT; SFP:1102; SCL:1; SRVR:CY1PR0301MB1225; H:az84smr01.freescale.net; FPR:; SPF:Fail; MLV:sfv; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Exchange-Diagnostics: 1; CY1PR0301MB1225; 2:v3+X5bmGiI7VcqzMtjCPFl12uiBf89afDgLIbobHHcxXg+iM/NWpIqapMS7NEQu8; 3:u+G4+cAc9uVX9SygDlbFAqR3KxtsXR5pSovsG97Iwrklym09+3/7DanbzVVu1gJejeKoBSqMrLg31sbPAdNRi3MC2OQAQ7MNvVfJGz/hSKPyqhTRRXb/S7zQyHKWxWfPeahiq5vF5nfGmYwNuGgwvc82ROxHBR1GIKNrRd4orQAdhfsNG6d+Kfz1LxitsGyX8zG1tuTQWv1ppW6TP4EtRxz9qdbzdlQqInNfxA2UZm0=; 25:8IhjVbNI8pstc+3Q7WMTcj/dblkC2GqRTy2+/+evHnty+Ig3ZXe3VbYXBXNiSf+bJnTDqrWq26/nWB7gjrHTBm45Y4qJVK1dnwwwCInMlsSUypIdoGAG4YM3vwtivTQbEoxsgfsf0950C2TToaxR7xRTUMLMXG1WF5AheoOuoLBOKp0noWpe9Z5NDawCjSG5K+3t1UPLEuywk1dqKBPBJgcp+D1/sm4khNt+cNN/BevpzzJ9HlbvEiLY5iUPz4gju6NxDTLkhy9nuy+KuIM9Rw==; 20:YryvBLox6iDzcYP3ne6Ax6GKWgriYDpJcE1h2glq2D7wzGXaXfhqD0bUbnI7bRWLEivqF9l7lRlhsjdixIZ3XrFxuyjpvwpzjv4pwJJ7HhV+yzLbFD2umEZ7L15eEY7etZWHKW2FDtuw9JYMgj4H00+eq1lOWp0V9QZqWQxE2UyfoilBA3zzvocC1u1EECcxMwpzBWMOV2hIoqUi2Z5tq3vPg4ChvaNKz59nfP+QAXQfkkmaK1FZG5CX6aF4s6dra4o76HTxLlFSe3obU5JrxddkKuFj7b+L3kEL737k4vQcvOvwVmHEVfHHtbaPrJY4UsQj5ZQZWfNlCDrkmslZ3Iejr20SBrUGe/AZt2zLSUY= X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:; SRVR:CY1PR0301MB1225; UriScan:; BCL:0; PCL:0; RULEID:; SRVR:CY1PR0301MB0700; X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-Test: UriScan:; X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(601004)(5005006)(3002001); SRVR:CY1PR0301MB1225; BCL:0; PCL:0; RULEID:; SRVR:CY1PR0301MB1225; X-Microsoft-Exchange-Diagnostics: 1; CY1PR0301MB1225; 4:Yn0G2dnFnWwGITH0Qc9ZiVp5xrHC4E+6cL9/H0cDxajKIP+CQ/hJxUsVMRk8oMPS1nPNIeoUWZaGEZn1EIWE7oVAp9VGGdCj1tXkHwq4lg1/Wrdrfb3TZAphXLbJrx3GmV51/9w12WNea1bo9narlkgE/3nsIkOFCbK8jIfqmJU0nX7PokCXRtsUrsvZwkfPFpPWz1CBGlRDuPQezvB5pFFOBr5CANPknWtpHmoiWYLvs1rf/ZxfYyXUXuJpXGZmjmEwVUC61LkN4arj9W9Qf/F5h2NGry7vYy3Wc/pwV0s= X-Forefront-PRVS: 0630013541 X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; CY1PR0301MB1225; 23:f9wVaw1b67nVaEdpQhVAI9e4LyWV5TvvwAn0gUY?= =?us-ascii?Q?XRvrCA33Kbl5JPo022QfhgUJA4ZxIXsqg5lfetQ8L8gLbXM3frGmxjpPiJ9P?= =?us-ascii?Q?hij37ZQMGcJVA4K9d5Q3N3910pOx+T5FPDFnfVAJVEZJzM5Kuc12W2yNAeEa?= =?us-ascii?Q?wSzpk7fbeyBxCV2cLMWO9WckJoObQ3s1dFRJmmBZPKuj3Dk0JTvZBhBAP0m5?= =?us-ascii?Q?e9HSgs9jwqDY+v1OcS0vIr5subG3DXSZj3exIIeiIuPYcArMMJtSc6noEZ3r?= =?us-ascii?Q?k+oSLUJxzFPuenPSzdI4pCahBHoEJ7bp9lVZRh3v+sQDdn2iADf673LM6jUz?= =?us-ascii?Q?WM0U3yjo1FrCnDa2H9kpt4YqIwBafHXK3NgfoktJRkHIhvAKnfosC3rOzwsS?= =?us-ascii?Q?c/vlGT0S4UGAlA+B+qEWKis29AjlrZitQQf5ptgbhleAPM1hNTdTcJMFX4Kl?= =?us-ascii?Q?scpaepVs88bgBBa3XqBF+4y92h6PJZa8mbFY33KMlhhYvVJEpc2SXMkzLMRi?= =?us-ascii?Q?dv2scRPXISzKVoZfI/rGA8pOr/BZTJjceh/bvYHyltarBxXn1njJLdlDhgDJ?= =?us-ascii?Q?sLTD3t2Z9vNGMRp53Dzxal6NK8mDWHFgqrf/2nfMR+uYd/6zv2UCCQgHJJ9X?= =?us-ascii?Q?f5mXpn+3LA45PWkYvXZYbxUXO4/Ts1RBT7edhxZFRtuMZ+x6EgxVGl4WG/xq?= =?us-ascii?Q?Oqe9v9iQ7LIV9sGyd6nyJR83wYOYkmq6wYDPQraqYcb8lims6M8jzhKdMrB/?= =?us-ascii?Q?ULlSmc8GbXhKLTfvFknrQILydl6GipnsCyHTRssFB3RWQ9QimJZYx9aSxmSE?= =?us-ascii?Q?89eBkMm4UWYeA74nofsrFT/roF3asrxOw+zcLdB+VITurc5EdDG3g0Xu8rUd?= =?us-ascii?Q?cIrk0OmxRYJfJ4rz6T0porPTlz2aYqruKX77P6pymCbpsZxr5jEZ83YFfj/e?= =?us-ascii?Q?DgKV5ke91pdtkua2EEuUtqW8B/DcFPpe9RMSIr4kcHJCioCxX31w/qmcl5+N?= =?us-ascii?Q?+OKi2CLNK6jMmbOVREwDnef8P?= X-Microsoft-Exchange-Diagnostics: 1; CY1PR0301MB1225; 5:Kgpf3rE47wqR9wg+0KOP4xCmE4/Xz2tDDFGuKAnH3n4NOh4WShbb7rPMBR1FP5HrA3BqfhnbBJDvjGiwK7mKaC+zS/vrpfM6RYH3773AFRxhvO+2xjlJjV7OUA65dmdGiMNwz7meHxLebPPmiu8dHQ==; 24:Fymyxut9Z9eGbTrtcZOTA3KZHV+zQPkHVgcSG/Elpxyy7RKXTP5FqzRYRUYnI36UZSZoY/v3l+35TVNsWYrTsOkTaPEZFzcmGUBNj0KO9CY=; 20:2tKr1NFAdfsJrqv43pRcVmOwKoVIAVmAGrbxFIvIPj0XXMdjWFYy9/1qvqcoQGg0htZ15ySK1RQoBmYNkvX6fw== X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jul 2015 19:18:01.1387 (UTC) X-MS-Exchange-CrossTenant-Id: 710a03f5-10f6-4d38-9ff4-a80b81da590d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=710a03f5-10f6-4d38-9ff4-a80b81da590d; Ip=[192.88.158.2]; Helo=[az84smr01.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR0301MB1225 X-Microsoft-Exchange-Diagnostics: 1; CY1PR0301MB0700; 2:ME4hUGWvDdvZYxsVr95LLDS1tYSWEgZ7HyOP354zBzK2NNEWJCqgr5/Nmg6ve3kD; 3:pVrdtUccuFZrK5B+7Hsqlz2sySUjyvfEy28Sl5pKmy3eihS9yj/LN6HXSb5AED6g6BpExZVYWEa5+t6JxtMzbQ2w3umlxIGqoadckdAVof14PK7IYcpWGJN8BgaHiXotYSKeldvpVDeHjGcE3aCbNv5+LWt+70XcaTy8yLV+DtzOakjxoJ6GTdZBhkFBSf1Er8wOhD5NqPfTP/9nmwDi6ALhnVibrjsq6uccW8GEUug=; 25:hkiy2tkX9KCGAjCQ9ddfp7CQp33N1PAJ80W5S03R1enAbdHwsYobdRr/IsOh67X5PpzN8OyWCw5o51F94CN4bUwZEvrviBOb+OYWpnhhTdf7Q0TDjV6zYZ7w4Upkyf6c7Rku3ETBYPmVpbp1cKwdTnFDO/2+jMmsLw3jcK9Q/2nv5tt3I3EdLxNrE7a/4dsKUGmkjENtwKjsfSQ2jsXxbh2EcjBqZFQ9ryMsEbeifwSVlZbeOITvUItuwxdvfVOncaWUF4ia2YxJ2jV0WG1nhg==; 23:DMYzXBzJPn5/GJjFz+RBHKqyHhrqYJCEG1oc21vh5WxgCfzsKDyp0zzeDwKCBx/an3tn/iO2Et084LQtziQsGVusSRanGJJILXAsbaJkUVObJ8F1IuDjwAgwreK2KsSGE7+FS0956mNPE4jpxzTeJ0VSqphei2TA4JONXjEKLsOSgRx8BehTzx6fA+22g5DGZi2kuucrnBHRSj0K4s+snnHmf4WjLk5hkYWmfDFrx2/Tb5vIm8D0aFHIZOH1TdH1 X-OriginatorOrg: freescale.com Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org * Extend pinctrl-imx driver to support iomux lpsr conntroller, * iMX7D has two iomuxc controllers, iomuxc controller similar as previous iMX SoC generation and iomuxc-lpsr which provides low power state rentetion capabilities on gpios that are part of iomuxc-lpsr (GPIO1_IO7..GPIO1_IO0). * Use IOMUXC_LPSR_SUPPORT and iput_val most significant bits to properly configure iomuxc/iomuxc-lpsr settings. Signed-off-by: Adrian Alonso - Change from v1 to v2: - Add suggested comment for input select register shared between iomuxc-lpsr and normal iomuxc controller. - Use IOMUXC_LPSR_MASK to extract pad group id and aling pin_id to 16 bit representation. - Change from v2 to v3 - Use devm_ioremap_resource instead of of_iomap to get iomuxc-lpsr base register address. Acked-by: frank.li@freescale.com --- drivers/pinctrl/freescale/pinctrl-imx.c | 72 ++++++++++++++++++++++----------- drivers/pinctrl/freescale/pinctrl-imx.h | 7 +++- 2 files changed, 55 insertions(+), 24 deletions(-) diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c index d7b98ba..aef4ca3 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.c +++ b/drivers/pinctrl/freescale/pinctrl-imx.c @@ -1,7 +1,7 @@ /* * Core driver for the imx pin controller * - * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. * Copyright (C) 2012 Linaro Ltd. * * Author: Dong Aisheng @@ -38,7 +38,6 @@ struct imx_pinctrl { struct device *dev; struct pinctrl_dev *pctl; - void __iomem *base; const struct imx_pinctrl_soc_info *info; }; @@ -212,12 +211,12 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, if (info->flags & SHARE_MUX_CONF_REG) { u32 reg; - reg = readl(ipctl->base + pin_reg->mux_reg); + reg = readl(pin_reg->base + pin_reg->mux_reg); reg &= ~(0x7 << 20); reg |= (pin->mux_mode << 20); - writel(reg, ipctl->base + pin_reg->mux_reg); + writel(reg, pin_reg->base + pin_reg->mux_reg); } else { - writel(pin->mux_mode, ipctl->base + pin_reg->mux_reg); + writel(pin->mux_mode, pin_reg->base + pin_reg->mux_reg); } dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n", pin_reg->mux_reg, pin->mux_mode); @@ -245,16 +244,22 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, * The input_reg[i] here is actually some IOMUXC general * purpose register, not regular select input register. */ - val = readl(ipctl->base + pin->input_reg); + val = readl(pin_reg->base + pin->input_reg); val &= ~mask; val |= select << shift; - writel(val, ipctl->base + pin->input_reg); + writel(val, pin_reg->base + pin->input_reg); } else if (pin->input_reg) { /* * Regular select input register can never be at offset * 0, and we only print register value for regular case. */ - writel(pin->input_val, ipctl->base + pin->input_reg); + if (info->flags & IOMUXC_LPSR_SUPPORT && + IOMUXC_LPSR_MASK(pin->input_val)) + /* iomuxc-lpsr select input register shared with normal iomuxc */ + writel(pin->input_val, info->base + pin->input_reg); + else + writel(pin->input_val, pin_reg->base + pin->input_reg); + dev_dbg(ipctl->dev, "==>select_input: offset 0x%x val 0x%x\n", pin->input_reg, pin->input_val); @@ -326,10 +331,10 @@ static int imx_pmx_gpio_request_enable(struct pinctrl_dev *pctldev, return -EINVAL; mux_pin: - reg = readl(ipctl->base + pin_reg->mux_reg); + reg = readl(pin_reg->base + pin_reg->mux_reg); reg &= ~(0x7 << 20); reg |= imx_pin->config; - writel(reg, ipctl->base + pin_reg->mux_reg); + writel(reg, pin_reg->base + pin_reg->mux_reg); return 0; } @@ -354,12 +359,12 @@ static int imx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, return -EINVAL; /* IBE always enabled allows us to read the value "on the wire" */ - reg = readl(ipctl->base + pin_reg->mux_reg); + reg = readl(pin_reg->base + pin_reg->mux_reg); if (input) reg &= ~0x2; else reg |= 0x2; - writel(reg, ipctl->base + pin_reg->mux_reg); + writel(reg, pin_reg->base + pin_reg->mux_reg); return 0; } @@ -386,7 +391,7 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev, return -EINVAL; } - *config = readl(ipctl->base + pin_reg->conf_reg); + *config = readl(pin_reg->base + pin_reg->conf_reg); if (info->flags & SHARE_MUX_CONF_REG) *config &= 0xffff; @@ -415,12 +420,12 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev, for (i = 0; i < num_configs; i++) { if (info->flags & SHARE_MUX_CONF_REG) { u32 reg; - reg = readl(ipctl->base + pin_reg->conf_reg); + reg = readl(pin_reg->base + pin_reg->conf_reg); reg &= ~0xffff; reg |= configs[i]; - writel(reg, ipctl->base + pin_reg->conf_reg); + writel(reg, pin_reg->base + pin_reg->conf_reg); } else { - writel(configs[i], ipctl->base + pin_reg->conf_reg); + writel(configs[i], pin_reg->base + pin_reg->conf_reg); } dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n", pin_reg->conf_reg, configs[i]); @@ -442,7 +447,7 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev, return; } - config = readl(ipctl->base + pin_reg->conf_reg); + config = readl(pin_reg->base + pin_reg->conf_reg); seq_printf(s, "0x%lx", config); } @@ -551,14 +556,25 @@ static int imx_pinctrl_parse_groups(struct device_node *np, } pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4; + + pin->input_reg = be32_to_cpu(*list++); + pin->mux_mode = be32_to_cpu(*list++); + pin->input_val = be32_to_cpu(*list++); + + if (info->flags & IOMUXC_LPSR_SUPPORT && + IOMUXC_LPSR_MASK(pin->input_val)) + pin_id = IOMUXC_LPSR_MASK(pin->input_val); + pin_reg = &info->pin_regs[pin_id]; pin->pin = pin_id; grp->pin_ids[i] = pin_id; pin_reg->mux_reg = mux_reg; pin_reg->conf_reg = conf_reg; - pin->input_reg = be32_to_cpu(*list++); - pin->mux_mode = be32_to_cpu(*list++); - pin->input_val = be32_to_cpu(*list++); + pin_reg->base = info->base; + + if (info->flags & IOMUXC_LPSR_SUPPORT && + IOMUXC_LPSR_MASK(pin->input_val)) + pin_reg->base = info->base_lpsr; /* SION bit is in mux register */ config = be32_to_cpu(*list++); @@ -709,9 +725,19 @@ int imx_pinctrl_probe(struct platform_device *pdev, } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - ipctl->base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(ipctl->base)) - return PTR_ERR(ipctl->base); + info->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(info->base)) + return PTR_ERR(info->base); + + if (info->flags & IOMUXC_LPSR_SUPPORT) { + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + info->base_lpsr = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(info->base_lpsr)) { + dev_err(&pdev->dev, + "iomuxc-lpsr base address not found\n"); + return PTR_ERR(info->base_lpsr); + } + } imx_pinctrl_desc.name = dev_name(&pdev->dev); imx_pinctrl_desc.pins = info->pins; diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h index 49e55d3..5e0f2e0 100644 --- a/drivers/pinctrl/freescale/pinctrl-imx.h +++ b/drivers/pinctrl/freescale/pinctrl-imx.h @@ -1,7 +1,7 @@ /* * IMX pinmux core definitions * - * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. * Copyright (C) 2012 Linaro Ltd. * * Author: Dong Aisheng @@ -69,6 +69,7 @@ struct imx_pmx_func { struct imx_pin_reg { s16 mux_reg; s16 conf_reg; + void __iomem *base; }; struct imx_pinctrl_soc_info { @@ -81,9 +82,13 @@ struct imx_pinctrl_soc_info { struct imx_pmx_func *functions; unsigned int nfunctions; unsigned int flags; + void __iomem *base; + void __iomem *base_lpsr; }; #define SHARE_MUX_CONF_REG 0x1 +#define IOMUXC_LPSR_SUPPORT 0x2 +#define IOMUXC_LPSR_MASK(id) ((id >> 0x10) & 0xffff) #define NO_MUX 0x0 #define NO_PAD 0x0