From patchwork Tue Jun 30 12:27:30 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Osmialowski X-Patchwork-Id: 489686 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 56C2A1402AA for ; Tue, 30 Jun 2015 22:33:00 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753179AbbF3McX (ORCPT ); Tue, 30 Jun 2015 08:32:23 -0400 Received: from fish.king.net.pl ([79.190.246.46]:56894 "EHLO king.net.pl" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752401AbbF3McJ (ORCPT ); Tue, 30 Jun 2015 08:32:09 -0400 Received: from localhost.localdomain (fish [127.0.0.1]) by king.net.pl (8.14.9/8.14.0) with ESMTP id t5UCSQiD028388 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Tue, 30 Jun 2015 14:28:27 +0200 Received: (from newchief@localhost) by localhost.localdomain (8.14.9/8.14.9/Submit) id t5UCSQRf028387; Tue, 30 Jun 2015 14:28:26 +0200 From: Paul Osmialowski To: Greg Kroah-Hartman , Ian Campbell , Jiri Slaby , Kumar Gala , Linus Walleij , Mark Rutland , Michael Turquette , Pawel Moll , Rob Herring , Russell King , Stephen Boyd , Vinod Koul , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, dmaengine@vger.kernel.org Cc: Arnd Bergmann , Geert Uytterhoeven , Nicolas Pitre , Paul Bolle , Thomas Gleixner , Uwe Kleine-Koenig , Paul Osmialowski , Anson Huang , Frank Li , Jingchang Lu , Rob Herring , Yuri Tikhonov , Sergei Poselenov , Alexander Potashev Subject: [PATCH v2 9/9] arm: twr-k70f120m: use Freescale lpuart driver with Kinetis SoC Date: Tue, 30 Jun 2015 14:27:30 +0200 Message-Id: <1435667250-28299-10-git-send-email-pawelo@king.net.pl> X-Mailer: git-send-email 2.3.6 In-Reply-To: <1435667250-28299-1-git-send-email-pawelo@king.net.pl> References: <1435667250-28299-1-git-send-email-pawelo@king.net.pl> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Note that enabling tx DMA resulted in messy output, so I didn't configure it in the .dts file - however nothing in the code prevents one from doing so. Also note that original reference UART driver from Emcraft did not implement tx DMA at all. Signed-off-by: Paul Osmialowski --- arch/arm/boot/dts/kinetis-twr-k70f120m.dts | 23 +++++++++ arch/arm/boot/dts/kinetis.dtsi | 78 ++++++++++++++++++++++++++++++ 2 files changed, 101 insertions(+) diff --git a/arch/arm/boot/dts/kinetis-twr-k70f120m.dts b/arch/arm/boot/dts/kinetis-twr-k70f120m.dts index a6efc29..5d8470a 100644 --- a/arch/arm/boot/dts/kinetis-twr-k70f120m.dts +++ b/arch/arm/boot/dts/kinetis-twr-k70f120m.dts @@ -10,11 +10,34 @@ model = "Freescale TWR-K70F120M Development Kit"; compatible = "fsl,kinetis-twr-k70f120m"; + chosen { + bootargs = "console=ttyLP2,115200"; + }; + memory { reg = <0x8000000 0x8000000>; }; }; +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "ok"; +}; + +&portE { + status = "ok"; + + uart2 { + uart2_pins: pinmux_uart2_pins { + fsl,pins = < + 16 0x300 /* E.16 = UART2_TX */ + 17 0x300 /* E.17 = UART2_RX */ + >; + }; + }; +}; + &pit0 { status = "ok"; }; diff --git a/arch/arm/boot/dts/kinetis.dtsi b/arch/arm/boot/dts/kinetis.dtsi index c2861f5..fedafe3 100644 --- a/arch/arm/boot/dts/kinetis.dtsi +++ b/arch/arm/boot/dts/kinetis.dtsi @@ -16,9 +16,87 @@ pmx3 = &portD; pmx4 = &portE; pmx5 = &portF; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; }; soc { + uart0: serial@4006a000 { + compatible = "fsl,kinetis-lpuart"; + reg = <0x4006a000 0x1000>; + interrupts = <45>, <46>; + interrupt-names = "uart-stat", "uart-err"; + clocks = <&mcg_cclk_gate 3 10>; + clock-names = "ipg"; + dmas = <&edma 0 2>; + dma-names = "rx"; + status = "disabled"; + }; + + uart1: serial@4006b000 { + compatible = "fsl,kinetis-lpuart"; + reg = <0x4006b000 0x1000>; + interrupts = <47>, <48>; + interrupt-names = "uart-stat", "uart-err"; + clocks = <&mcg_cclk_gate 3 11>; + clock-names = "ipg"; + dmas = <&edma 0 4>; + dma-names = "rx"; + status = "disabled"; + }; + + uart2: serial@4006c000 { + compatible = "fsl,kinetis-lpuart"; + reg = <0x4006c000 0x1000>; + interrupts = <49>, <50>; + interrupt-names = "uart-stat", "uart-err"; + clocks = <&mcg_pclk_gate 3 12>; + clock-names = "ipg"; + dmas = <&edma 0 6>; + dma-names = "rx"; + status = "disabled"; + }; + + uart3: serial@4006d000 { + compatible = "fsl,kinetis-lpuart"; + reg = <0x4006d000 0x1000>; + interrupts = <51>, <52>; + interrupt-names = "uart-stat", "uart-err"; + clocks = <&mcg_pclk_gate 3 13>; + clock-names = "ipg"; + dmas = <&edma 0 8>; + dma-names = "rx"; + status = "disabled"; + }; + + uart4: serial@400ea000 { + compatible = "fsl,kinetis-lpuart"; + reg = <0x400ea000 0x1000>; + interrupts = <53>, <54>; + interrupt-names = "uart-stat", "uart-err"; + clocks = <&mcg_pclk_gate 0 10>; + clock-names = "ipg"; + dmas = <&edma 0 10>; + dma-names = "rx"; + status = "disabled"; + }; + + uart5: serial@400eb000 { + compatible = "fsl,kinetis-lpuart"; + reg = <0x400eb000 0x1000>; + interrupts = <55>, <56>; + interrupt-names = "uart-stat", "uart-err"; + clocks = <&mcg_pclk_gate 0 11>; + clock-names = "ipg"; + dmas = <&edma 0 12>; + dma-names = "rx"; + status = "disabled"; + }; + edma: dma-controller@40008000 { compatible = "fsl,kinetis-edma"; reg = <0x40008000 0x2000>, /* DMAC */