From patchwork Sat May 9 07:53:50 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Coquelin X-Patchwork-Id: 470297 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 9865914018C for ; Sat, 9 May 2015 17:59:41 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=f9YmRcNN; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752936AbbEIH7R (ORCPT ); Sat, 9 May 2015 03:59:17 -0400 Received: from mail-wi0-f180.google.com ([209.85.212.180]:35209 "EHLO mail-wi0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753831AbbEIHya (ORCPT ); Sat, 9 May 2015 03:54:30 -0400 Received: by widdi4 with SMTP id di4so53124737wid.0; Sat, 09 May 2015 00:54:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eU9Pbpy5UcNtF5zwqgl5kV/wA+B1v2uKLg9oq5t/psA=; b=f9YmRcNNPWqqiSbaK+CIMz014rfwAtdNUymXKRsd+zm4FG+IoRQ2Bj4QktHMN+nlC5 TDXHR1wjpLKu+JtZ+OpjJdTY0HC98+n1L7vpCw+5hLk0ptt5yzv5sfA5Zd9uFq0bnsVU JVEF/M5vgNOL4Sz3Dvi7k5zokbfOIwEf2H/gl3eljFGncPkkQ8jPRIdrTGDbyHtAAOcp LmhqUgzbYaWjpH4RCxWbUaSVHl+xRTfnIu7u2nHR/UNJeUQWCgjgFpl9GMZDGJ6KP3+6 qhEzehuuii6sghgvhxX/LznzSX2/VhpOyT6PMvyW8IkbJ5QEIibp6Zfnqsdz3vau38dj TtLA== X-Received: by 10.180.80.10 with SMTP id n10mr4440326wix.82.1431158068370; Sat, 09 May 2015 00:54:28 -0700 (PDT) Received: from lmecul0520.st.com. (213.143.7.84.rev.sfr.net. [84.7.143.213]) by mx.google.com with ESMTPSA id z12sm12098020wjq.12.2015.05.09.00.54.25 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 09 May 2015 00:54:27 -0700 (PDT) From: Maxime Coquelin To: u.kleine-koenig@pengutronix.de, afaerber@suse.de, geert@linux-m68k.org, Rob Herring , Philipp Zabel , Linus Walleij , Arnd Bergmann , stefan@agner.ch, pmeerw@pmeerw.net, pebolle@tiscali.nl, peter@hurleysoftware.com, andy.shevchenko@gmail.com, cw00.choi@samsung.com, Russell King , Daniel Lezcano , joe@perches.com, Vladimir Zapolskiy , lee.jones@linaro.org, Daniel Thompson Cc: Jonathan Corbet , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Andrew Morton , "David S. Miller" , Mauro Carvalho Chehab , Antti Palosaari , Tejun Heo , Will Deacon , Nikolay Borisov , Rusty Russell , Kees Cook , Michal Marek , linux-doc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, mcoquelin.stm32@gmail.com, Nicolae Rosia , Kamil Lulko Subject: [PATCH v8 08/16] dt-bindings: Document the STM32 timer bindings Date: Sat, 9 May 2015 09:53:50 +0200 Message-Id: <1431158038-3813-9-git-send-email-mcoquelin.stm32@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1431158038-3813-1-git-send-email-mcoquelin.stm32@gmail.com> References: <1431158038-3813-1-git-send-email-mcoquelin.stm32@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This adds documentation of device tree bindings for the STM32 timer. Tested-by: Chanwoo Choi Acked-by: Rob Herring Signed-off-by: Maxime Coquelin --- .../devicetree/bindings/timer/st,stm32-timer.txt | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/st,stm32-timer.txt diff --git a/Documentation/devicetree/bindings/timer/st,stm32-timer.txt b/Documentation/devicetree/bindings/timer/st,stm32-timer.txt new file mode 100644 index 0000000..8ef28e7 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/st,stm32-timer.txt @@ -0,0 +1,22 @@ +. STMicroelectronics STM32 timer + +The STM32 MCUs family has several general-purpose 16 and 32 bits timers. + +Required properties: +- compatible : Should be "st,stm32-timer" +- reg : Address and length of the register set +- clocks : Reference on the timer input clock +- interrupts : Reference to the timer interrupt + +Optional properties: +- resets: Reference to a reset controller asserting the timer + +Example: + +timer5: timer@40000c00 { + compatible = "st,stm32-timer"; + reg = <0x40000c00 0x400>; + interrupts = <50>; + resets = <&rrc 259>; + clocks = <&clk_pmtr1>; +};