From patchwork Fri Apr 3 21:16:06 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joachim Eastwood X-Patchwork-Id: 458074 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id B45781400B7 for ; Sat, 4 Apr 2015 08:16:50 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="verification failed; unprotected key" header.d=gmail.com header.i=@gmail.com header.b=pDLTxanl; dkim-adsp=none (unprotected policy); dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752559AbbDCVQs (ORCPT ); Fri, 3 Apr 2015 17:16:48 -0400 Received: from mail-la0-f45.google.com ([209.85.215.45]:33921 "EHLO mail-la0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752112AbbDCVQr (ORCPT ); Fri, 3 Apr 2015 17:16:47 -0400 Received: by lagg8 with SMTP id g8so86449847lag.1; Fri, 03 Apr 2015 14:16:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5N0mRhaCe3rReixnwbELfVMfCYjPE+HQYtsYJA62vQ4=; b=pDLTxanlLiuWVswLuU4WwxXjmcOQwdqfFpPGshe8ySxLkcm70jvGbs1Yk9xfOx7WWn cy3PWEdoQcDIY2NaHEANMxGqn4iW2CqgezYAV8v76Tz8L/tsIiIxYGwkHmq4pCEOh8S8 XMGxmgVa96cJEmKKgd6z0oohAiK6+TDkptmYm0fv2RTa0a3GozfcwMqg5EOqM6Cp+4p5 Z/JhjaxKFETtWKkelL4CQUx/nqLJKV/wsV1YyGY2oqEm5VgGcvjCsQUbpJrrFFL4L6JU asFDwrBpBLmysTyOnAMJkh16q0s8zlRA2r+urzxlkVucq4trNUSPd4WnOntiUt6e4wMa 45Kw== X-Received: by 10.112.27.163 with SMTP id u3mr3579649lbg.75.1428095805700; Fri, 03 Apr 2015 14:16:45 -0700 (PDT) Received: from localhost.localdomain ([90.149.48.183]) by mx.google.com with ESMTPSA id lf12sm1015786lac.38.2015.04.03.14.16.44 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Fri, 03 Apr 2015 14:16:45 -0700 (PDT) From: Joachim Eastwood To: linus.walleij@linaro.org, gnurou@gmail.com, linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: arnd@arndb.de, devicetree@vger.kernel.org, ariel.dalessandro@gmail.com, ezequiel@vanguardiasur.com.ar, Joachim Eastwood Subject: [PATCH 5/6] ARM: dts: lpc18xx: add pinctrl and gpio nodes Date: Fri, 3 Apr 2015 23:16:06 +0200 Message-Id: <1428095767-6286-6-git-send-email-manabian@gmail.com> X-Mailer: git-send-email 1.8.0 In-Reply-To: <1428095767-6286-1-git-send-email-manabian@gmail.com> References: <1428095767-6286-1-git-send-email-manabian@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Signed-off-by: Joachim Eastwood Acked-by: Linus Walleij --- arch/arm/boot/dts/lpc18xx.dtsi | 57 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/arch/arm/boot/dts/lpc18xx.dtsi b/arch/arm/boot/dts/lpc18xx.dtsi index 8e9f51c88fad..e0099a7793b9 100644 --- a/arch/arm/boot/dts/lpc18xx.dtsi +++ b/arch/arm/boot/dts/lpc18xx.dtsi @@ -16,6 +16,9 @@ #include "dt-bindings/clock/lpc18xx-cgu.h" #include "dt-bindings/clock/lpc18xx-ccu.h" +#define LPC_PIN(port, pin) (0x##port * 32 + pin) +#define LPC_GPIO(port, pin) (port * 32 + pin) + / { aliases { serial0 = &uart0; @@ -148,6 +151,12 @@ clocks = <&ccu1 CLK_CPU_TIMER1>; }; + pinctrl: scu@40086000 { + compatible = "nxp,lpc1850-scu"; + reg = <0x40086000 0x1000>; + clocks = <&ccu1 CLK_CPU_SCU>; + }; + uart2: serial@400c1000 { compatible = "ns16550a"; reg = <0x400c1000 0x1000>; @@ -181,5 +190,53 @@ interrupts = <15>; clocks = <&ccu1 CLK_CPU_TIMER3>; }; + + gpio: gpio@400f4000 { + compatible = "nxp,lpc1850-gpio"; + reg = <0x400f4000 0x4000>; + clocks = <&ccu1 CLK_CPU_GPIO>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>, + <&pinctrl LPC_GPIO(0,4) LPC_PIN(1,0) 1>, + <&pinctrl LPC_GPIO(0,8) LPC_PIN(1,1) 4>, + <&pinctrl LPC_GPIO(1,8) LPC_PIN(1,5) 2>, + <&pinctrl LPC_GPIO(1,0) LPC_PIN(1,7) 8>, + <&pinctrl LPC_GPIO(0,2) LPC_PIN(1,15) 2>, + <&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>, + <&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>, + <&pinctrl LPC_GPIO(5,0) LPC_PIN(2,0) 7>, + <&pinctrl LPC_GPIO(0,7) LPC_PIN(2,7) 1>, + <&pinctrl LPC_GPIO(5,7) LPC_PIN(2,8) 1>, + <&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9) 1>, + <&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>, + <&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>, + <&pinctrl LPC_GPIO(5,8) LPC_PIN(3,1) 2>, + <&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4) 2>, + <&pinctrl LPC_GPIO(0,6) LPC_PIN(3,6) 1>, + <&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7) 2>, + <&pinctrl LPC_GPIO(2,0) LPC_PIN(4,0) 7>, + <&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8) 3>, + <&pinctrl LPC_GPIO(2,9) LPC_PIN(5,0) 7>, + <&pinctrl LPC_GPIO(2,7) LPC_PIN(5,7) 1>, + <&pinctrl LPC_GPIO(3,0) LPC_PIN(6,1) 5>, + <&pinctrl LPC_GPIO(0,5) LPC_PIN(6,6) 1>, + <&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7) 2>, + <&pinctrl LPC_GPIO(3,5) LPC_PIN(6,9) 3>, + <&pinctrl LPC_GPIO(2,8) LPC_PIN(6,12) 1>, + <&pinctrl LPC_GPIO(3,8) LPC_PIN(7,0) 8>, + <&pinctrl LPC_GPIO(4,0) LPC_PIN(8,0) 8>, + <&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0) 4>, + <&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4) 2>, + <&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6) 1>, + <&pinctrl LPC_GPIO(4,8) LPC_PIN(a,1) 3>, + <&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4) 1>, + <&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0) 7>, + <&pinctrl LPC_GPIO(6,0) LPC_PIN(c,1) 14>, + <&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>, + <&pinctrl LPC_GPIO(7,0) LPC_PIN(e,0) 16>, + <&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1) 3>, + <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>; + }; }; };