From patchwork Tue Mar 3 14:41:08 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Petazzoni X-Patchwork-Id: 445731 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id A70371400DE for ; Wed, 4 Mar 2015 01:41:37 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756768AbbCCOlf (ORCPT ); Tue, 3 Mar 2015 09:41:35 -0500 Received: from down.free-electrons.com ([37.187.137.238]:39055 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1755976AbbCCOle (ORCPT ); Tue, 3 Mar 2015 09:41:34 -0500 Received: by mail.free-electrons.com (Postfix, from userid 106) id C02813B4; Tue, 3 Mar 2015 15:41:32 +0100 (CET) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail.free-electrons.com X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED,SHORTCIRCUIT, URIBL_BLOCKED shortcircuit=ham autolearn=disabled version=3.4.0 Received: from localhost (col31-4-88-188-83-94.fbx.proxad.net [88.188.83.94]) by mail.free-electrons.com (Postfix) with ESMTPSA id 11670381; Tue, 3 Mar 2015 15:41:32 +0100 (CET) From: Thomas Petazzoni To: Jason Cooper , Andrew Lunn , Sebastian Hesselbarth , Gregory Clement , devicetree@vger.kernel.org, Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Mike Turquette , Stephen Boyd , Linus Walleij Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, Tawfik Bayouk , Nadav Haklai , Lior Amsalem , Ezequiel Garcia , Maxime Ripard , Thomas Petazzoni Subject: [PATCH v3 13/20] clk: mvebu: extend common code to allow an optional refclk Date: Tue, 3 Mar 2015 15:41:08 +0100 Message-Id: <1425393675-17820-14-git-send-email-thomas.petazzoni@free-electrons.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1425393675-17820-1-git-send-email-thomas.petazzoni@free-electrons.com> References: <1425393675-17820-1-git-send-email-thomas.petazzoni@free-electrons.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The Armada 39x, contrary to its predecessor, has a configurable reference clock frequency, of either 25 Mhz, or 40 Mhz. For the previous SoCs, it was fixed to 25 Mhz and described directly as such in the Device Tree. For Armada 39x, we need to read certain registers to know whether the frequency is 25 or 40 Mhz. Therefore, this commit extends the common mvebu clock code to allow the SoC-specific code to say it wants to register a reference clock, by giving a non-NULL ->get_refclk_freq() function pointer in its coreclk_soc_desc structure. Signed-off-by: Thomas Petazzoni --- drivers/clk/mvebu/common.c | 17 +++++++++++++++++ drivers/clk/mvebu/common.h | 1 + 2 files changed, 18 insertions(+) diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c index 0d4d121..15b370f 100644 --- a/drivers/clk/mvebu/common.c +++ b/drivers/clk/mvebu/common.c @@ -121,6 +121,11 @@ void __init mvebu_coreclk_setup(struct device_node *np, /* Allocate struct for TCLK, cpu clk, and core ratio clocks */ clk_data.clk_num = 2 + desc->num_ratios; + + /* One more clock for the optional refclk */ + if (desc->get_refclk_freq) + clk_data.clk_num += 1; + clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *), GFP_KERNEL); if (WARN_ON(!clk_data.clks)) { @@ -162,6 +167,18 @@ void __init mvebu_coreclk_setup(struct device_node *np, WARN_ON(IS_ERR(clk_data.clks[2+n])); }; + /* Register optional refclk */ + if (desc->get_refclk_freq) { + const char *name = "refclk"; + of_property_read_string_index(np, "clock-output-names", + 2 + desc->num_ratios, &name); + rate = desc->get_refclk_freq(base); + clk_data.clks[2 + desc->num_ratios] = + clk_register_fixed_rate(NULL, name, NULL, + CLK_IS_ROOT, rate); + WARN_ON(IS_ERR(clk_data.clks[2 + desc->num_ratios])); + } + /* SAR register isn't needed anymore */ iounmap(base); diff --git a/drivers/clk/mvebu/common.h b/drivers/clk/mvebu/common.h index 783b563..f0de6c8 100644 --- a/drivers/clk/mvebu/common.h +++ b/drivers/clk/mvebu/common.h @@ -30,6 +30,7 @@ struct coreclk_soc_desc { u32 (*get_tclk_freq)(void __iomem *sar); u32 (*get_cpu_freq)(void __iomem *sar); void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div); + u32 (*get_refclk_freq)(void __iomem *sar); bool (*is_sscg_enabled)(void __iomem *sar); u32 (*fix_sscg_deviation)(u32 system_clk); const struct coreclk_ratio *ratios;