| Message ID | 1424455277-29983-11-git-send-email-mcoquelin.stm32@gmail.com |
|---|---|
| State | New |
| Headers | show |
On Fri, Feb 20, 2015 at 7:01 PM, Maxime Coquelin <mcoquelin.stm32@gmail.com> wrote: > This adds documentation of device tree bindings for the > STM32 pin controller. > > Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> (...) > +Pin controller node: > +Required properies: > +- compatible : "st,stm32-pinctrl" > +- #address-cells: The value of this property must be 1 > +- #size-cells : The value of this property must be 1 > +- ranges : defines mapping between pin controller node (parent) to > + gpio-bank node (children). > + > +GPIO controller/bank node: > +Required properties: > +- gpio-controller : Indicates this device is a GPIO controller > +- #gpio-cells : Should be two. > + The first cell is the pin number > + The second one is the polarity: > + - 0 for active high > + - 1 for active low > +- reg : The gpio address range, relative to the pinctrl range > +- st,bank-name : Should be a name string for this bank as specified in > + the datasheet OK... (...) > + ... > + pin-functions nodes follow... > + }; > + > +Contents of function subnode node: > +---------------------------------- > + > +Required properties for pin configuration node: > +- st,pins : Child node with list of pins with configuration. Don't use vendor prefix. Use the new standard notation, just "pins". See Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt > +Below is the format of how each pin conf should look like. > + > +<bank offset altmode pull type speed> > + > +Every PIO is represented with 4 to 6 parameters. > +Each parameter is explained as below. > + > +- bank : Should be bank phandle to which this PIO belongs. > +- offset : Offset in the PIO bank. No. Don't hardcode register offsets into the DTS files. This is something the driver should know from the compatible string or instance number, not by explicit reference. > +- altmode : Should be mode or alternate function number associated this pin, as > +described in the datasheet (IN, OUT, ALT0...ALT15, ANALOG) > +- pull : Should be either NO_PULL, PULL_UP or PULL_DOWN > +- type : Should be either PUSH_PULL or OPEN_DRAIN. > + Setting it is not needed for IN and ANALOG modes, or alternate > + functions acting as inputs. > +- speed : Value taken from the datasheet, depending on the function > +(LOW_SPEED, MEDIUM_SPEED, FAST_SPEED, HIGH_SPEED) > + Setting it is not needed for IN and ANALOG modes, or alternate > + functions acting as inputs. NACK. Make your Kconfig select GENERIC_PINCONF and use the already existing generic pin configuration specifiers from the standard bindings. Like bias-pull-up; etc. This kind of custom pin config is a thing of the past. > +usart1 { > + pinctrl_usart1: usart1-0 { > + st,pins { > + tx = <&gpioa 9 ALT7 NO_PULL PUSH_PULL LOW_SPEED>; > + rx = <&gpioa 10 ALT7 NO_PULL PUSH_PULL LOW_SPEED>; > + }; > + }; > +}; You might have to use separate parameters for muxing and config in your description. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
I saw this other thing: On Fri, Feb 20, 2015 at 7:01 PM, Maxime Coquelin <mcoquelin.stm32@gmail.com> wrote: > This adds documentation of device tree bindings for the > STM32 pin controller. > > Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> (...) > +- altmode : Should be mode or alternate function number associated this pin, as > +described in the datasheet (IN, OUT, ALT0...ALT15, ANALOG) We can now describe muxing (altmodes etc) in two ways as described in the generic bindings in Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt This is done by strings combining a function with N groups. We are also discussing having a single config number setting up all and keeping down the size of the DTB (which is close to what you're doing here). Please take part in that discussion to standardize such bindings. Sascha Hauer and others are involved, don't know the exact topic right now but it involved using a single "pinmux" parameter in the device treel. All agree on using the standardized pin config bindings henceforth so start by migrating to these. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-stm32.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-stm32.txt new file mode 100644 index 0000000..0fb5b24 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-stm32.txt @@ -0,0 +1,99 @@ +* STM32 GPIO and Pin Mux/Config controller + +STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware +controller. It controls the input/output settings on the available pins and +also provides ability to multiplex and configure the output of various on-chip +controllers onto these pads. + +Pin controller node: +Required properies: +- compatible : "st,stm32-pinctrl" +- #address-cells: The value of this property must be 1 +- #size-cells : The value of this property must be 1 +- ranges : defines mapping between pin controller node (parent) to + gpio-bank node (children). + +GPIO controller/bank node: +Required properties: +- gpio-controller : Indicates this device is a GPIO controller +- #gpio-cells : Should be two. + The first cell is the pin number + The second one is the polarity: + - 0 for active high + - 1 for active low +- reg : The gpio address range, relative to the pinctrl range +- st,bank-name : Should be a name string for this bank as specified in + the datasheet + +Optional properties: +- reset: : Reference to the reset controller + +Example: +#include <dt-bindings/pinctrl/pinctrl-stm32.h> +... + + pin-controller { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32-pinctrl"; + ranges = <0 0x40020000 0x3000>; + + gpioa: gpio@40020000 { + gpio-controller; + #gpio-cells = <2>; + reg = <0x0 0x400>; + resets = <&reset_ahb1 0>; + st,bank-name = "GPIOA"; + }; + ... + pin-functions nodes follow... + }; + +Contents of function subnode node: +---------------------------------- + +Required properties for pin configuration node: +- st,pins : Child node with list of pins with configuration. + +Below is the format of how each pin conf should look like. + +<bank offset altmode pull type speed> + +Every PIO is represented with 4 to 6 parameters. +Each parameter is explained as below. + +- bank : Should be bank phandle to which this PIO belongs. +- offset : Offset in the PIO bank. +- altmode : Should be mode or alternate function number associated this pin, as +described in the datasheet (IN, OUT, ALT0...ALT15, ANALOG) +- pull : Should be either NO_PULL, PULL_UP or PULL_DOWN +- type : Should be either PUSH_PULL or OPEN_DRAIN. + Setting it is not needed for IN and ANALOG modes, or alternate + functions acting as inputs. +- speed : Value taken from the datasheet, depending on the function +(LOW_SPEED, MEDIUM_SPEED, FAST_SPEED, HIGH_SPEED) + Setting it is not needed for IN and ANALOG modes, or alternate + functions acting as inputs. + +usart1 { + pinctrl_usart1: usart1-0 { + st,pins { + tx = <&gpioa 9 ALT7 NO_PULL PUSH_PULL LOW_SPEED>; + rx = <&gpioa 10 ALT7 NO_PULL PUSH_PULL LOW_SPEED>; + }; + }; +}; + +adc2 { + pinctrl_adc2: adc2-0 { + st,pins { + adc0 = <&gpioe 4 ANALOG NO_PULL>; + }; + }; +}; + +usart1: usart@40011000 { + ... + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usart1>; +};
This adds documentation of device tree bindings for the STM32 pin controller. Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> --- .../devicetree/bindings/pinctrl/pinctrl-stm32.txt | 99 ++++++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/pinctrl-stm32.txt