| Message ID | 1423763164-5606-7-git-send-email-mcoquelin.stm32@gmail.com |
|---|---|
| State | New |
| Headers | show |
Am 12.02.2015 um 18:45 schrieb Maxime Coquelin: > The STM32 MCUs family IP can be reset by accessing some shared registers. > > The specificity is that some reset lines are used by the timers. > At timer initialization time, the timer has to be reset, that's why > we cannot use a regular driver. > > Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> > --- > .../devicetree/bindings/reset/st,stm32-reset.txt | 19 ++++ > drivers/reset/Makefile | 1 + > drivers/reset/reset-stm32.c | 124 +++++++++++++++++++++ > 3 files changed, 144 insertions(+) > create mode 100644 Documentation/devicetree/bindings/reset/st,stm32-reset.txt > create mode 100644 drivers/reset/reset-stm32.c > > diff --git a/Documentation/devicetree/bindings/reset/st,stm32-reset.txt b/Documentation/devicetree/bindings/reset/st,stm32-reset.txt > new file mode 100644 > index 0000000..add1298 > --- /dev/null > +++ b/Documentation/devicetree/bindings/reset/st,stm32-reset.txt > @@ -0,0 +1,19 @@ > +STMicroelectronics STM32 Peripheral Reset Controller > +==================================================== > + > +Please also refer to reset.txt in this directory for common reset > +controller binding usage. > + > +Required properties: > +- compatible: Should be "st,stm32-reset" > +- reg: should be register base and length as documented in the > + datasheet > +- #reset-cells: 1, see below > + > +example: > + > +reset_ahb1: reset@40023810 { > + #reset-cells = <1>; > + compatible = "st,stm32-reset"; > + reg = <0x40023810 0x4>; > +}; [snip] RM0090 has two different chapters on the RCC IP: * Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) * Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) I therefore feel it is wrong to use "stm32-" here; instead I used "st,stm32f429-rcc" (also relates to 12/14 discussion). This may apply to other identifiers, too. Regards, Andreas
2015-02-16 0:59 GMT+01:00 Andreas Färber <afaerber@suse.de>: > Am 12.02.2015 um 18:45 schrieb Maxime Coquelin: >> The STM32 MCUs family IP can be reset by accessing some shared registers. >> >> The specificity is that some reset lines are used by the timers. >> At timer initialization time, the timer has to be reset, that's why >> we cannot use a regular driver. >> >> Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> >> --- >> .../devicetree/bindings/reset/st,stm32-reset.txt | 19 ++++ >> drivers/reset/Makefile | 1 + >> drivers/reset/reset-stm32.c | 124 +++++++++++++++++++++ >> 3 files changed, 144 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/reset/st,stm32-reset.txt >> create mode 100644 drivers/reset/reset-stm32.c >> >> diff --git a/Documentation/devicetree/bindings/reset/st,stm32-reset.txt b/Documentation/devicetree/bindings/reset/st,stm32-reset.txt >> new file mode 100644 >> index 0000000..add1298 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/reset/st,stm32-reset.txt >> @@ -0,0 +1,19 @@ >> +STMicroelectronics STM32 Peripheral Reset Controller >> +==================================================== >> + >> +Please also refer to reset.txt in this directory for common reset >> +controller binding usage. >> + >> +Required properties: >> +- compatible: Should be "st,stm32-reset" >> +- reg: should be register base and length as documented in the >> + datasheet >> +- #reset-cells: 1, see below >> + >> +example: >> + >> +reset_ahb1: reset@40023810 { >> + #reset-cells = <1>; >> + compatible = "st,stm32-reset"; >> + reg = <0x40023810 0x4>; >> +}; > [snip] > > RM0090 has two different chapters on the RCC IP: > * Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) > * Reset and clock control for STM32F405xx/07xx and STM32F415xx/17xx(RCC) > > I therefore feel it is wrong to use "stm32-" here; instead I used > "st,stm32f429-rcc" (also relates to 12/14 discussion). This may apply to > other identifiers, too. In this first version, the reset driver was really generic, and was compatible with the STM32 family. The only difference would have been in the device trees. Now, from the discussion with Philipp, I will reconsider the implementation to add some named constants, so maybe I will reconsider the compatible, it will depend on how I will implement it. Thanks, Maxime > > Regards, > Andreas > > -- > SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany > GF: Felix Imendörffer, Jane Smithard, Jennifer Guild, Dilip Upmanyu, > Graham Norton; HRB 21284 (AG Nürnberg) -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/reset/st,stm32-reset.txt b/Documentation/devicetree/bindings/reset/st,stm32-reset.txt new file mode 100644 index 0000000..add1298 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/st,stm32-reset.txt @@ -0,0 +1,19 @@ +STMicroelectronics STM32 Peripheral Reset Controller +==================================================== + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Required properties: +- compatible: Should be "st,stm32-reset" +- reg: should be register base and length as documented in the + datasheet +- #reset-cells: 1, see below + +example: + +reset_ahb1: reset@40023810 { + #reset-cells = <1>; + compatible = "st,stm32-reset"; + reg = <0x40023810 0x4>; +}; diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 157d421..aed12d1 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -1,5 +1,6 @@ obj-$(CONFIG_RESET_CONTROLLER) += core.o obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o +obj-$(CONFIG_ARCH_STM32) += reset-stm32.o obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o obj-$(CONFIG_ARCH_STI) += sti/ diff --git a/drivers/reset/reset-stm32.c b/drivers/reset/reset-stm32.c new file mode 100644 index 0000000..7a96677 --- /dev/null +++ b/drivers/reset/reset-stm32.c @@ -0,0 +1,124 @@ +/* + * Copyright (C) Maxime Coquelin 2015 + * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> + * License terms: GNU General Public License (GPL), version 2 + * + * Heavily based on sunxi driver from Maxime Ripard. + */ + +#include <linux/err.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> +#include <linux/reset-controller.h> +#include <linux/slab.h> +#include <linux/spinlock.h> +#include <linux/types.h> + +struct stm32_reset_data { + spinlock_t lock; + void __iomem *membase; + struct reset_controller_dev rcdev; +}; + +static int stm32_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct stm32_reset_data *data = container_of(rcdev, + struct stm32_reset_data, + rcdev); + int bank = id / BITS_PER_LONG; + int offset = id % BITS_PER_LONG; + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&data->lock, flags); + + reg = readl_relaxed(data->membase + (bank * 4)); + writel_relaxed(reg | BIT(offset), data->membase + (bank * 4)); + + spin_unlock_irqrestore(&data->lock, flags); + + return 0; +} + +static int stm32_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct stm32_reset_data *data = container_of(rcdev, + struct stm32_reset_data, + rcdev); + int bank = id / BITS_PER_LONG; + int offset = id % BITS_PER_LONG; + unsigned long flags; + u32 reg; + + spin_lock_irqsave(&data->lock, flags); + + reg = readl_relaxed(data->membase + (bank * 4)); + writel_relaxed(reg & ~BIT(offset), data->membase + (bank * 4)); + + spin_unlock_irqrestore(&data->lock, flags); + + return 0; +} + +static struct reset_control_ops stm32_reset_ops = { + .assert = stm32_reset_assert, + .deassert = stm32_reset_deassert, +}; + +static void stm32_reset_init(struct device_node *np) +{ + struct stm32_reset_data *data; + struct resource res; + resource_size_t size; + int err; + + data = kzalloc(sizeof(*data), GFP_KERNEL); + if (!data) + return; + + err = of_address_to_resource(np, 0, &res); + if (err) + goto err_alloc; + + size = resource_size(&res); + if (!request_mem_region(res.start, size, np->name)) { + err = -EINVAL; + goto err_alloc; + } + + data->membase = ioremap(res.start, size); + if (!data->membase) { + err = -ENOMEM; + goto err_alloc; + } + + spin_lock_init(&data->lock); + + data->rcdev.owner = THIS_MODULE; + data->rcdev.nr_resets = size * 8; + data->rcdev.ops = &stm32_reset_ops; + data->rcdev.of_node = np; + + err = reset_controller_register(&data->rcdev); + if (err) + goto err_iomap; + + pr_info("%s: %d reset lines registered\n", np->full_name, + data->rcdev.nr_resets); + return; + +err_iomap: + iounmap(data->membase); +err_alloc: + kfree(data); + pr_err("%s: Reset ctrl registration failed (%d).\n", + np->full_name, err); +} + +RESET_CONTROLLER_OF_DECLARE(stm32, "st,stm32-reset", stm32_reset_init); +
The STM32 MCUs family IP can be reset by accessing some shared registers. The specificity is that some reset lines are used by the timers. At timer initialization time, the timer has to be reset, that's why we cannot use a regular driver. Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com> --- .../devicetree/bindings/reset/st,stm32-reset.txt | 19 ++++ drivers/reset/Makefile | 1 + drivers/reset/reset-stm32.c | 124 +++++++++++++++++++++ 3 files changed, 144 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/st,stm32-reset.txt create mode 100644 drivers/reset/reset-stm32.c