From patchwork Sat Jan 17 18:15:16 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Beniamino Galvani X-Patchwork-Id: 430127 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 26A1214017F for ; Sun, 18 Jan 2015 05:17:04 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752660AbbAQSQk (ORCPT ); Sat, 17 Jan 2015 13:16:40 -0500 Received: from mail-wi0-f178.google.com ([209.85.212.178]:37001 "EHLO mail-wi0-f178.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752382AbbAQSQj (ORCPT ); Sat, 17 Jan 2015 13:16:39 -0500 Received: by mail-wi0-f178.google.com with SMTP id z2so9411692wiv.5; Sat, 17 Jan 2015 10:16:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=S/fZWamUy486ZiBZ87h9XlAKyZBKQrUGWUhgyTv+Acs=; b=WZbUrccFH39ry+ALhfmYr4wiHHWRznJBkOUMe9DjxTCoiGSRUgTALVI78zVRQwtiRH ULkyJiiaryiJc4lPzS4O5lLI/wlOflZtLLMLlOGenVZG/Uy0zHtn0e/UH46zIDTa7uxF bwfjmlXdpn3NtIYVvHWWrA9Om+5vgmanWeYdWMvg98s0gWDy1AFftH6y4RjCLTB/MkeZ bOyuRz2OanOG02BD1DUpolUFf97ToUxgLQL55IaoVmAenmOyPm6em2Y37APtfylCX20O s1lGbvn2TTPmsvVapvAiIJcUdkhZ5l9yLdvKIeUbqFQtLkAVQjUGNZUNuRWXYlAlnORB czDg== X-Received: by 10.180.98.3 with SMTP id ee3mr18573913wib.12.1421518597489; Sat, 17 Jan 2015 10:16:37 -0800 (PST) Received: from localhost.localdomain ([95.236.99.95]) by mx.google.com with ESMTPSA id gl5sm11052002wib.0.2015.01.17.10.16.34 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sat, 17 Jan 2015 10:16:36 -0800 (PST) From: Beniamino Galvani To: Linus Walleij , Carlo Caione Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Arnd Bergmann , Russell King , Soren Brinkmann , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Jerry Cao , Victor Wan , Beniamino Galvani Subject: [PATCH v4 3/3] ARM: dts: meson8: add pinctrl node Date: Sat, 17 Jan 2015 19:15:16 +0100 Message-Id: <1421518516-26976-4-git-send-email-b.galvani@gmail.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1421518516-26976-1-git-send-email-b.galvani@gmail.com> References: <1421518516-26976-1-git-send-email-b.galvani@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add pinctrl node to the DTSI file for meson8 and sub-nodes for some standard mux configurations. Signed-off-by: Beniamino Galvani --- arch/arm/boot/dts/meson8.dtsi | 68 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 1f442a7..a2ddcb8 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -43,6 +43,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include /include/ "meson.dtsi" / { @@ -89,4 +90,71 @@ compatible = "fixed-clock"; clock-frequency = <141666666>; }; + + pinctrl: pinctrl@c1109880 { + compatible = "amlogic,meson8-pinctrl"; + reg = <0xc1109880 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio: banks@c11080b0 { + reg = <0xc11080b0 0x28>, + <0xc11080e8 0x18>, + <0xc1108120 0x18>, + <0xc1108030 0x30>; + reg-names = "mux", "pull", "pull-enable", "gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio_ao: ao-bank@c1108030 { + reg = <0xc8100014 0x4>, + <0xc810002c 0x4>, + <0xc8100024 0x8>; + reg-names = "mux", "pull", "gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + + uart_ao_a_pins: uart_ao_a { + mux { + groups = "uart_tx_ao_a", "uart_rx_ao_a"; + function = "uart_ao"; + }; + }; + + i2c_ao_pins: i2c_mst_ao { + mux { + groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao"; + function = "i2c_mst_ao"; + }; + }; + + spi_nor_pins: nor { + mux { + groups = "nor_d", "nor_q", "nor_c", "nor_cs"; + function = "nor"; + }; + }; + + ir_recv_pins: remote { + mux { + groups = "remote_input"; + function = "remote"; + }; + }; + + eth_pins: ethernet { + mux { + groups = "eth_tx_clk_50m", "eth_tx_en", + "eth_txd1", "eth_txd0", + "eth_rx_clk_in", "eth_rx_dv", + "eth_rxd1", "eth_rxd0", "eth_mdio", + "eth_mdc"; + function = "ethernet"; + }; + }; + }; + }; /* end of / */