From patchwork Wed Dec 24 09:23:36 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sherlock Wang X-Patchwork-Id: 423886 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 807FC1400D5 for ; Wed, 24 Dec 2014 20:25:29 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751642AbaLXJZ3 (ORCPT ); Wed, 24 Dec 2014 04:25:29 -0500 Received: from mail-pd0-f177.google.com ([209.85.192.177]:60663 "EHLO mail-pd0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751336AbaLXJZ2 (ORCPT ); Wed, 24 Dec 2014 04:25:28 -0500 Received: by mail-pd0-f177.google.com with SMTP id ft15so9569853pdb.22 for ; Wed, 24 Dec 2014 01:25:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=K2gMqQIaFO59ghp+MJtTjIL64CwnOgnOYA8G2ag3NQo=; b=DxB+fXFlCOqFYO2HaMSZww/c9/cFDlZ/khWKDnESn+BXNv4Nn8cL90mT1hv0ygIJaE JZp04wQoGom8G1p3Y5DeuKnN4UGMcI9XVqkhKS2JR0PlJN9TpUyxYD+H224Ush7Cy34O df4mC4Tw0LPIbM8S5ACr8PXKFzU/UwgImKqNlpsMTraPhXG4Tp8udzYcHgyNE25i2VRp 5OWfh+gNbOR4qFo+3O367Jcwn+V/A1NDX20H7ER7KYUnmVJP7Rqi3agfkAaNQX8AsT1k +bKbMZK/F15fWojpS5d3b1akmaVDl4jHpQrnwZOW3WGxB9Os8+rYhrkuyXbb33cGbFKS aQdg== X-Received: by 10.70.119.71 with SMTP id ks7mr51466945pdb.140.1419413127379; Wed, 24 Dec 2014 01:25:27 -0800 (PST) Received: from localhost.localdomain ([58.251.159.252]) by mx.google.com with ESMTPSA id dn2sm1138684pdb.12.2014.12.24.01.25.19 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 24 Dec 2014 01:25:26 -0800 (PST) From: Zhou Wang To: Haojian Zhuang , Wei Xu , Linus Walleij , Alexandre Courbot , Arnd Bergmann , Olof Johansson , Russell King Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, wangzhou1@hisilicon.com, liguozhu@hisilicon.com, Zhou Wang Subject: [PATCH v5 2/2] ARM: dts: hip04: add GPIO pieces Date: Wed, 24 Dec 2014 17:23:36 +0800 Message-Id: <1419413016-31932-3-git-send-email-wangzhou.bry@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1419413016-31932-1-git-send-email-wangzhou.bry@gmail.com> References: <1419413016-31932-1-git-send-email-wangzhou.bry@gmail.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Hisilicon Soc hip04 has four GPIO controllers, each one has 32 GPIOs and can be configured to be an interrupt controller.The GPIO controllers are compatible with the snps,dw-apb-gpio driver. This patch add the corresponding device tree nodes. Signed-off-by: Zhou Wang --- arch/arm/boot/dts/hip04.dtsi | 75 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm/boot/dts/hip04.dtsi b/arch/arm/boot/dts/hip04.dtsi index 2388145..267942a 100644 --- a/arch/arm/boot/dts/hip04.dtsi +++ b/arch/arm/boot/dts/hip04.dtsi @@ -269,6 +269,81 @@ interrupts = <0 372 4>; }; + gpio@4003000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x4003000 0x1000>; + + gpio3: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 392 4>; + }; + }; + + gpio@4002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x4002000 0x1000>; + + gpio2: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 391 4>; + }; + }; + + gpio@4001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x4001000 0x1000>; + + gpio1: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 390 4>; + }; + }; + + gpio@4000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0x4000000 0x1000>; + + gpio0: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <32>; + reg = <0>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 389 4>; + }; + }; }; etb@0,e3c42000 {