From patchwork Thu Mar 9 16:22:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julia Cartwright X-Patchwork-Id: 737083 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vfHpz3HJ7z9s87 for ; Fri, 10 Mar 2017 04:45:15 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932472AbdCIRpN (ORCPT ); Thu, 9 Mar 2017 12:45:13 -0500 Received: from mx0a-00010702.pphosted.com ([148.163.156.75]:39538 "EHLO mx0b-00010702.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932808AbdCIRpM (ORCPT ); Thu, 9 Mar 2017 12:45:12 -0500 Received: from pps.filterd (m0098780.ppops.net [127.0.0.1]) by mx0a-00010702.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v29GKrqQ022537; Thu, 9 Mar 2017 10:22:15 -0600 Received: from ni.com (skprod2.natinst.com [130.164.80.23]) by mx0a-00010702.pphosted.com with ESMTP id 2933r6sp93-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 09 Mar 2017 10:22:14 -0600 Received: from us-aus-exhub1.ni.corp.natinst.com (us-aus-exhub1.ni.corp.natinst.com [130.164.68.41]) by us-aus-skprod2.natinst.com (8.16.0.17/8.16.0.17) with ESMTPS id v29GMDCZ008770 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 9 Mar 2017 10:22:13 -0600 Received: from us-aus-exch3.ni.corp.natinst.com (130.164.68.13) by us-aus-exhub1.ni.corp.natinst.com (130.164.68.41) with Microsoft SMTP Server (TLS) id 15.0.1156.6; Thu, 9 Mar 2017 10:22:13 -0600 Received: from us-aus-exhub1.ni.corp.natinst.com (130.164.68.41) by us-aus-exch3.ni.corp.natinst.com (130.164.68.13) with Microsoft SMTP Server (TLS) id 15.0.1156.6; Thu, 9 Mar 2017 10:22:13 -0600 Received: from jcartwri.amer.corp.natinst.com (130.164.49.7) by us-aus-exhub1.ni.corp.natinst.com (130.164.68.41) with Microsoft SMTP Server id 15.0.1156.6 via Frontend Transport; Thu, 9 Mar 2017 10:22:13 -0600 Received: by jcartwri.amer.corp.natinst.com (Postfix, from userid 1000) id 5E01530111D; Thu, 9 Mar 2017 10:22:13 -0600 (CST) From: Julia Cartwright To: Linus Walleij CC: , Thomas Gleixner , Subject: [PATCH 17/19] pinctrl: amd: make use of raw_spinlock variants Date: Thu, 9 Mar 2017 10:22:04 -0600 Message-ID: <1078eff36a2507d1aa5130cc0a9b28d520aabf31.1489015238.git.julia@ni.com> X-Mailer: git-send-email 2.11.1 In-Reply-To: References: MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-03-09_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1702020001 definitions=main-1703090122 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-03-09_13:, , signatures=0 X-Proofpoint-Spam-Details: rule=notspam policy=default score=30 priorityscore=1501 malwarescore=0 suspectscore=2 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=30 reason=mlx scancount=1 engine=8.0.1-1702020001 definitions=main-1703090122 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The amd pinctrl drivers currently implement an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by: Julia Cartwright --- drivers/pinctrl/pinctrl-amd.c | 66 +++++++++++++++++++++---------------------- drivers/pinctrl/pinctrl-amd.h | 2 +- 2 files changed, 34 insertions(+), 34 deletions(-) diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index d69e357a7a98..043ac9bcbccb 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -41,11 +41,11 @@ static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) u32 pin_reg; struct amd_gpio *gpio_dev = gpiochip_get_data(gc); - spin_lock_irqsave(&gpio_dev->lock, flags); + raw_spin_lock_irqsave(&gpio_dev->lock, flags); pin_reg = readl(gpio_dev->base + offset * 4); pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); writel(pin_reg, gpio_dev->base + offset * 4); - spin_unlock_irqrestore(&gpio_dev->lock, flags); + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); return 0; } @@ -57,7 +57,7 @@ static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, unsigned long flags; struct amd_gpio *gpio_dev = gpiochip_get_data(gc); - spin_lock_irqsave(&gpio_dev->lock, flags); + raw_spin_lock_irqsave(&gpio_dev->lock, flags); pin_reg = readl(gpio_dev->base + offset * 4); pin_reg |= BIT(OUTPUT_ENABLE_OFF); if (value) @@ -65,7 +65,7 @@ static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, else pin_reg &= ~BIT(OUTPUT_VALUE_OFF); writel(pin_reg, gpio_dev->base + offset * 4); - spin_unlock_irqrestore(&gpio_dev->lock, flags); + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); return 0; } @@ -76,9 +76,9 @@ static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) unsigned long flags; struct amd_gpio *gpio_dev = gpiochip_get_data(gc); - spin_lock_irqsave(&gpio_dev->lock, flags); + raw_spin_lock_irqsave(&gpio_dev->lock, flags); pin_reg = readl(gpio_dev->base + offset * 4); - spin_unlock_irqrestore(&gpio_dev->lock, flags); + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); return !!(pin_reg & BIT(PIN_STS_OFF)); } @@ -89,14 +89,14 @@ static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) unsigned long flags; struct amd_gpio *gpio_dev = gpiochip_get_data(gc); - spin_lock_irqsave(&gpio_dev->lock, flags); + raw_spin_lock_irqsave(&gpio_dev->lock, flags); pin_reg = readl(gpio_dev->base + offset * 4); if (value) pin_reg |= BIT(OUTPUT_VALUE_OFF); else pin_reg &= ~BIT(OUTPUT_VALUE_OFF); writel(pin_reg, gpio_dev->base + offset * 4); - spin_unlock_irqrestore(&gpio_dev->lock, flags); + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); } static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, @@ -108,7 +108,7 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, unsigned long flags; struct amd_gpio *gpio_dev = gpiochip_get_data(gc); - spin_lock_irqsave(&gpio_dev->lock, flags); + raw_spin_lock_irqsave(&gpio_dev->lock, flags); pin_reg = readl(gpio_dev->base + offset * 4); if (debounce) { @@ -159,7 +159,7 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, pin_reg &= ~DB_CNTRl_MASK; } writel(pin_reg, gpio_dev->base + offset * 4); - spin_unlock_irqrestore(&gpio_dev->lock, flags); + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); return ret; } @@ -224,9 +224,9 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) } for (; i < pin_num; i++) { seq_printf(s, "pin%d\t", i); - spin_lock_irqsave(&gpio_dev->lock, flags); + raw_spin_lock_irqsave(&gpio_dev->lock, flags); pin_reg = readl(gpio_dev->base + i * 4); - spin_unlock_irqrestore(&gpio_dev->lock, flags); + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { interrupt_enable = "interrupt is enabled|"; @@ -331,12 +331,12 @@ static void amd_gpio_irq_enable(struct irq_data *d) struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct amd_gpio *gpio_dev = gpiochip_get_data(gc); - spin_lock_irqsave(&gpio_dev->lock, flags); + raw_spin_lock_irqsave(&gpio_dev->lock, flags); pin_reg = readl(gpio_dev->base + (d->hwirq)*4); pin_reg |= BIT(INTERRUPT_ENABLE_OFF); pin_reg |= BIT(INTERRUPT_MASK_OFF); writel(pin_reg, gpio_dev->base + (d->hwirq)*4); - spin_unlock_irqrestore(&gpio_dev->lock, flags); + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); } static void amd_gpio_irq_disable(struct irq_data *d) @@ -346,12 +346,12 @@ static void amd_gpio_irq_disable(struct irq_data *d) struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct amd_gpio *gpio_dev = gpiochip_get_data(gc); - spin_lock_irqsave(&gpio_dev->lock, flags); + raw_spin_lock_irqsave(&gpio_dev->lock, flags); pin_reg = readl(gpio_dev->base + (d->hwirq)*4); pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); pin_reg &= ~BIT(INTERRUPT_MASK_OFF); writel(pin_reg, gpio_dev->base + (d->hwirq)*4); - spin_unlock_irqrestore(&gpio_dev->lock, flags); + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); } static void amd_gpio_irq_mask(struct irq_data *d) @@ -361,11 +361,11 @@ static void amd_gpio_irq_mask(struct irq_data *d) struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct amd_gpio *gpio_dev = gpiochip_get_data(gc); - spin_lock_irqsave(&gpio_dev->lock, flags); + raw_spin_lock_irqsave(&gpio_dev->lock, flags); pin_reg = readl(gpio_dev->base + (d->hwirq)*4); pin_reg &= ~BIT(INTERRUPT_MASK_OFF); writel(pin_reg, gpio_dev->base + (d->hwirq)*4); - spin_unlock_irqrestore(&gpio_dev->lock, flags); + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); } static void amd_gpio_irq_unmask(struct irq_data *d) @@ -375,11 +375,11 @@ static void amd_gpio_irq_unmask(struct irq_data *d) struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct amd_gpio *gpio_dev = gpiochip_get_data(gc); - spin_lock_irqsave(&gpio_dev->lock, flags); + raw_spin_lock_irqsave(&gpio_dev->lock, flags); pin_reg = readl(gpio_dev->base + (d->hwirq)*4); pin_reg |= BIT(INTERRUPT_MASK_OFF); writel(pin_reg, gpio_dev->base + (d->hwirq)*4); - spin_unlock_irqrestore(&gpio_dev->lock, flags); + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); } static void amd_gpio_irq_eoi(struct irq_data *d) @@ -389,11 +389,11 @@ static void amd_gpio_irq_eoi(struct irq_data *d) struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct amd_gpio *gpio_dev = gpiochip_get_data(gc); - spin_lock_irqsave(&gpio_dev->lock, flags); + raw_spin_lock_irqsave(&gpio_dev->lock, flags); reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); reg |= EOI_MASK; writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); - spin_unlock_irqrestore(&gpio_dev->lock, flags); + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); } static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) @@ -404,7 +404,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct amd_gpio *gpio_dev = gpiochip_get_data(gc); - spin_lock_irqsave(&gpio_dev->lock, flags); + raw_spin_lock_irqsave(&gpio_dev->lock, flags); pin_reg = readl(gpio_dev->base + (d->hwirq)*4); /* Ignore the settings coming from the client and @@ -469,7 +469,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; writel(pin_reg, gpio_dev->base + (d->hwirq)*4); - spin_unlock_irqrestore(&gpio_dev->lock, flags); + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); return ret; } @@ -511,14 +511,14 @@ static void amd_gpio_irq_handler(struct irq_desc *desc) chained_irq_enter(chip, desc); /*enable GPIO interrupt again*/ - spin_lock_irqsave(&gpio_dev->lock, flags); + raw_spin_lock_irqsave(&gpio_dev->lock, flags); reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); reg64 = reg; reg64 = reg64 << 32; reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0); reg64 |= reg; - spin_unlock_irqrestore(&gpio_dev->lock, flags); + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); /* * first 46 bits indicates interrupt status. @@ -546,11 +546,11 @@ static void amd_gpio_irq_handler(struct irq_desc *desc) if (handled == 0) handle_bad_irq(desc); - spin_lock_irqsave(&gpio_dev->lock, flags); + raw_spin_lock_irqsave(&gpio_dev->lock, flags); reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); reg |= EOI_MASK; writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); - spin_unlock_irqrestore(&gpio_dev->lock, flags); + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); chained_irq_exit(chip, desc); } @@ -602,9 +602,9 @@ static int amd_pinconf_get(struct pinctrl_dev *pctldev, struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); enum pin_config_param param = pinconf_to_config_param(*config); - spin_lock_irqsave(&gpio_dev->lock, flags); + raw_spin_lock_irqsave(&gpio_dev->lock, flags); pin_reg = readl(gpio_dev->base + pin*4); - spin_unlock_irqrestore(&gpio_dev->lock, flags); + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); switch (param) { case PIN_CONFIG_INPUT_DEBOUNCE: arg = pin_reg & DB_TMR_OUT_MASK; @@ -644,7 +644,7 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, enum pin_config_param param; struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); - spin_lock_irqsave(&gpio_dev->lock, flags); + raw_spin_lock_irqsave(&gpio_dev->lock, flags); for (i = 0; i < num_configs; i++) { param = pinconf_to_config_param(configs[i]); arg = pinconf_to_config_argument(configs[i]); @@ -683,7 +683,7 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, writel(pin_reg, gpio_dev->base + pin*4); } - spin_unlock_irqrestore(&gpio_dev->lock, flags); + raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); return ret; } @@ -751,7 +751,7 @@ static int amd_gpio_probe(struct platform_device *pdev) if (!gpio_dev) return -ENOMEM; - spin_lock_init(&gpio_dev->lock); + raw_spin_lock_init(&gpio_dev->lock); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { diff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h index c03f77822069..5b1cb965c767 100644 --- a/drivers/pinctrl/pinctrl-amd.h +++ b/drivers/pinctrl/pinctrl-amd.h @@ -87,7 +87,7 @@ struct amd_function { }; struct amd_gpio { - spinlock_t lock; + raw_spinlock_t lock; void __iomem *base; const struct amd_pingroup *groups;