Message ID | 20240917-lan969x-pinctrl-v2-0-ea02cbc56831@microchip.com |
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Headers | show
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17 Sep 2024 05:46:20 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Tue, 17 Sep 2024 05:45:55 -0700 Received: from DEN-DL-M70577.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Tue, 17 Sep 2024 05:45:53 -0700 From: Daniel Machon <daniel.machon@microchip.com> Subject: [PATCH v2 0/2] pinctrl: ocelot: add support for lan969x SoC Date: Tue, 17 Sep 2024 14:45:39 +0200 Message-ID: <20240917-lan969x-pinctrl-v2-0-ea02cbc56831@microchip.com> Precedence: bulk X-Mailing-List: linux-gpio@vger.kernel.org List-Id: <linux-gpio.vger.kernel.org> List-Subscribe: <mailto:linux-gpio+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-gpio+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAPN56WYC/2WNyw6CMBQFf4V0bU2pBVNX/odh0cfV3gRabKHBE P7dQuLK5STnzKwkQURI5FatJELGhMEX4KeKGKf8CyjawoQzLpisOe2Vl61c6IjeTLGnwsimMQz 0lbWkvMYIT1wO46MrrFUCqqPyxu0eC5m+Z5hh3zpMU4ifI57r/fHriL9Orimjtb4oYUUjNLP3A U0MxuF4NmEg3bZtXyiyPFLOAAAA To: Linus Walleij <linus.walleij@linaro.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Alexandre Belloni <alexandre.belloni@bootlin.com>, Lars Povlsen <lars.povlsen@microchip.com>, Horatiu Vultur <horatiu.vultur@microchip.com>, Steen Hegelund <Steen.Hegelund@microchip.com> CC: <linux-gpio@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org> X-Mailer: b4 0.14-dev |
Series |
pinctrl: ocelot: add support for lan969x SoC
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On Tue, Sep 17, 2024 at 2:46 PM Daniel Machon <daniel.machon@microchip.com> wrote: > This series adds support for lan969x SoC pinctrl by reusing the existing > Ocelot pinctrl driver. > > There are 66 General Purpose I/O pins that are individually configurable > to multiple interfaces. The matrix of available GPIO alternate functions > is detailed in the pinmuxing table of patch #2. > > Patch #1 adds compatible strings for lan969x in the dt-bindings. > Patch #2 adds support for lan969x SoC pinctrl. > > Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Bindings ACKed and no reaction from other maintainers for two weeks, so patches applied! Yours, Linus Walleij
This series adds support for lan969x SoC pinctrl by reusing the existing Ocelot pinctrl driver. There are 66 General Purpose I/O pins that are individually configurable to multiple interfaces. The matrix of available GPIO alternate functions is detailed in the pinmuxing table of patch #2. Patch #1 adds compatible strings for lan969x in the dt-bindings. Patch #2 adds support for lan969x SoC pinctrl. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> --- Changes in v2: - dt-bindings: add only microchip,lan9691-pinctrl to conditional enum. - Link to v1: https://lore.kernel.org/r/20240914-lan969x-pinctrl-v1-0-1b3a4d454b0d@microchip.com --- Daniel Machon (2): dt-bindings: ocelot: document lan969x-pinctrl pinctrl: ocelot: add support for lan969x SoC pinctrl .../bindings/pinctrl/mscc,ocelot-pinctrl.yaml | 27 ++- drivers/pinctrl/pinctrl-ocelot.c | 203 +++++++++++++++++++++ 2 files changed, 222 insertions(+), 8 deletions(-) --- base-commit: 3cfb5aa10cb78571e214e48a3a6e42c11d5288a1 change-id: 20240912-lan969x-pinctrl-4c955c0eb706 Best regards,