| Message ID | 20241023104406.4083460-1-billy_tsai@aspeedtech.com |
|---|---|
| State | New |
| Headers | show |
| Series | pinctrl: aspeed-g6: Support drive-strength for GPIOF/G | expand |
On Wed, 2024-10-23 at 18:44 +0800, Billy Tsai wrote: > Add drive strength configuration support for GPIO F and G groups. > > Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
On Wed, Oct 23, 2024 at 12:44 PM Billy Tsai <billy_tsai@aspeedtech.com> wrote: > Add drive strength configuration support for GPIO F and G groups. > > Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Patch applied. Yours, Linus Walleij
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c index 6ecc656abc44..5a7cd0a88687 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -2607,6 +2607,10 @@ static struct aspeed_pin_config aspeed_g6_configs[] = { { PIN_CONFIG_DRIVE_STRENGTH, { AB8, AB8 }, SCU454, GENMASK(27, 26)}, /* LAD0 */ { PIN_CONFIG_DRIVE_STRENGTH, { AB7, AB7 }, SCU454, GENMASK(25, 24)}, + /* GPIOF */ + { PIN_CONFIG_DRIVE_STRENGTH, { D22, A23 }, SCU458, GENMASK(9, 8)}, + /* GPIOG */ + { PIN_CONFIG_DRIVE_STRENGTH, { E21, B21 }, SCU458, GENMASK(11, 10)}, /* MAC3 */ { PIN_CONFIG_POWER_SOURCE, { H24, E26 }, SCU458, BIT_MASK(4)},
Add drive strength configuration support for GPIO F and G groups. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> --- drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 4 ++++ 1 file changed, 4 insertions(+)