Message ID | 20240919094339.2407641-7-billy_tsai@aspeedtech.com |
---|---|
State | New |
Headers | show
Return-Path: <linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org> X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org (client-ip=2404:9400:2:0:216:3eff:fee1:b9f1; helo=lists.ozlabs.org; envelope-from=linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org; receiver=patchwork.ozlabs.org) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2404:9400:2:0:216:3eff:fee1:b9f1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4X8Vw723WJz1y1m for <incoming@patchwork.ozlabs.org>; Thu, 19 Sep 2024 19:44:07 +1000 (AEST) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4X8Vw46sMjz30WT for <incoming@patchwork.ozlabs.org>; Thu, 19 Sep 2024 19:44:04 +1000 (AEST) X-Original-To: linux-aspeed@lists.ozlabs.org Delivered-To: linux-aspeed@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; arc=none smtp.remote-ip=211.20.114.72 ARC-Seal: i=1; a=rsa-sha256; d=lists.ozlabs.org; s=201707; t=1726739040; cv=none; b=Q7GchQhJPCgSYVdQ5mUBmI1S1SFQhq3ZSwvSUSmqCMGtCym2ku5/LaLjQgFVJlA3hL8UCmHu0S6qM3m0XjVFLkEL1+b8FI4HaDse/Phl9p5yUQo37dsOeF6NcQLUYnwEnu+qv6GaEQV4B4ATYBe1b3sGbBLVXK8cwvCrM4w77y04jly4Hmes50P+nWfKe+gu281x98r/VDvpV/9FTPa8FZhu7jqGj3MIlzI0PJKK5ndSk3Vh6vM23CKayfrqxDDtK5G3FFEP7UTe5BYzY/B3y6Zi+4CAcuJZPar67HraCufz7TffuE4x3JKus5MXJxK1mxxxXMMpxMhnC00B8kgGTg== ARC-Message-Signature: i=1; a=rsa-sha256; d=lists.ozlabs.org; s=201707; t=1726739040; c=relaxed/relaxed; bh=PXBR3WqY/xe8pQcWnDs1WNF7sGixG/iaEUh4WPOry8Y=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gMLJy7YNmiF1G661iDr70rQd+zf+7SEMFtlADWG7UcitiwwvwiSppcpizb078/9UoYxN1+MTdNqI8zzU29hYC6x7zMRkurzglDEqps/Fi/qm1rPEb9LfDJQEFXWL7Z5Uys2SjlIzafluMCyiUlAdCUAcEQ1I1QmsRkdxqctZHixNgABXVwUUz5wDcXhOezjVOtf75leYwagGaglC0porAn5R71qOLT03AEGLjHO/pmYfndoRUYEVVeIiz+E2Haca4rK1cOzT4jRL4PLoupbDc9Y+Ywd/l9a1StMrRxelc9J9mPgAPeDWBPiBHdYvatWXfE6xfli7RmmRE/CTvLueOw== ARC-Authentication-Results: i=1; lists.ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com; spf=pass (client-ip=211.20.114.72; helo=twmbx01.aspeed.com; envelope-from=billy_tsai@aspeedtech.com; receiver=lists.ozlabs.org) smtp.mailfrom=aspeedtech.com Authentication-Results: lists.ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=aspeedtech.com Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=aspeedtech.com (client-ip=211.20.114.72; helo=twmbx01.aspeed.com; envelope-from=billy_tsai@aspeedtech.com; receiver=lists.ozlabs.org) Received: from TWMBX01.aspeed.com (mail.aspeedtech.com [211.20.114.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4X8Vw02MvMz2y66 for <linux-aspeed@lists.ozlabs.org>; Thu, 19 Sep 2024 19:44:00 +1000 (AEST) Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.12; Thu, 19 Sep 2024 17:43:39 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1258.12 via Frontend Transport; Thu, 19 Sep 2024 17:43:39 +0800 From: Billy Tsai <billy_tsai@aspeedtech.com> To: <linus.walleij@linaro.org>, <brgl@bgdev.pl>, <robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>, <joel@jms.id.au>, <andrew@codeconstruct.com.au>, <linux-gpio@vger.kernel.org>, <devicetree@vger.kernel.org>, <linux-arm-kernel@lists.infradead.org>, <linux-aspeed@lists.ozlabs.org>, <linux-kernel@vger.kernel.org>, <BMC-SW@aspeedtech.com>, <Peter.Yin@quantatw.com>, <Jay_Zhang@wiwynn.com> Subject: [PATCH v4 6/6] gpio: aspeed: Add the flush write to ensure the write complete. Date: Thu, 19 Sep 2024 17:43:39 +0800 Message-ID: <20240919094339.2407641-7-billy_tsai@aspeedtech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240919094339.2407641-1-billy_tsai@aspeedtech.com> References: <20240919094339.2407641-1-billy_tsai@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux ASPEED SoC development <linux-aspeed.lists.ozlabs.org> List-Unsubscribe: <https://lists.ozlabs.org/options/linux-aspeed>, <mailto:linux-aspeed-request@lists.ozlabs.org?subject=unsubscribe> List-Archive: <http://lists.ozlabs.org/pipermail/linux-aspeed/> List-Post: <mailto:linux-aspeed@lists.ozlabs.org> List-Help: <mailto:linux-aspeed-request@lists.ozlabs.org?subject=help> List-Subscribe: <https://lists.ozlabs.org/listinfo/linux-aspeed>, <mailto:linux-aspeed-request@lists.ozlabs.org?subject=subscribe> Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" <linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org> |
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Add Aspeed G7 gpio support
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expand
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diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c index c811e84db0b9..daa12e21d946 100644 --- a/drivers/gpio/gpio-aspeed.c +++ b/drivers/gpio/gpio-aspeed.c @@ -400,6 +400,8 @@ static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, struct aspeed_gpio *gpio = gpiochip_get_data(gc); gpio->config->llops->reg_bit_set(gpio, offset, reg_val, val); + // flush write + gpio->config->llops->reg_bits_get(gpio, offset, reg_val); } static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset,
Performing a dummy read ensures that the register write operation is fully completed, mitigating any potential bus delays that could otherwise impact the frequency of bitbang usage. E.g., if the JTAG application uses GPIO to control the JTAG pins (TCK, TMS, TDI, TDO, and TRST), and the application sets the TCK clock to 1 MHz, the GPIO’s high/low transitions will rely on a delay function to ensure the clock frequency does not exceed 1 MHz. However, this can lead to rapid toggling of the GPIO because the write operation is POSTed and does not wait for a bus acknowledgment. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> --- drivers/gpio/gpio-aspeed.c | 2 ++ 1 file changed, 2 insertions(+)