diff mbox series

[v2,2/4] dt-bindings: misc: Aspeed coprocessor interrupt controller

Message ID 20180618045902.11453-3-benh@kernel.crashing.org
State Superseded, archived
Headers show
Series arm: dts: Aspeed SoC device-tree update | expand

Commit Message

Benjamin Herrenschmidt June 18, 2018, 4:59 a.m. UTC 
Add the device-tree binding definition for the AST2400
and AST2500 coprocessor interrupt controller

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
 .../devicetree/bindings/misc/aspeed,cvic.txt  | 35 +++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/misc/aspeed,cvic.txt

Comments

Joel Stanley June 19, 2018, 6:56 a.m. UTC | #1 
On 18 June 2018 at 14:29, Benjamin Herrenschmidt
<benh@kernel.crashing.org> wrote:
> Add the device-tree binding definition for the AST2400
> and AST2500 coprocessor interrupt controller
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
>  .../devicetree/bindings/misc/aspeed,cvic.txt  | 35 +++++++++++++++++++
>  1 file changed, 35 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/misc/aspeed,cvic.txt
>
> diff --git a/Documentation/devicetree/bindings/misc/aspeed,cvic.txt b/Documentation/devicetree/bindings/misc/aspeed,cvic.txt
> new file mode 100644
> index 000000000000..2562e2991e4d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/misc/aspeed,cvic.txt

Is there a reason you didn't put this in bindings/interrupt-controller?

Aside from that this looks good.

> @@ -0,0 +1,35 @@
> +* Aspeed AST2400 and AST2500 coprocessor interrupt controller
> +
> +This file describes the bindings for the interrupt controller present
> +in the AST2400 and AST2500 BMC SoCs which provides interrupt to the
> +ColdFire coprocessor.
> +
> +It is not a normal interrupt controller and it would be rather
> +inconvenient to create an interrupt tree for it as it somewhat shares
> +some of the same sources as the main ARM interrupt controller but with
> +different numbers.
> +
> +The AST2500 supports a SW generated interrupt
> +
> +Required properties:
> +- reg: address and length of the register for the device.
> +- compatible: "aspeed,cvic" and one of:
> +               "aspeed,ast2400-cvic"
> +             or
> +               "aspeed,ast2500-cvic"
> +
> +- valid-sources: One cell, bitmap of supported sources for the implementation
> +
> +Optional properties;
> +- copro-sw-interrupts: List of interrupt numbers that can be used as
> +                      SW interrupts from the ARM to the coprocessor.
> +                      (AST2500 only)
> +
> +Example:
> +
> +       cvic: copro-interrupt-controller@1e6c2000 {
> +               compatible = "aspeed,ast2500-cvic";
> +               valid-sources = <0xffffffff>;
> +               copro-sw-interrupts = <1>;
> +               reg = <0x1e6c2000 0x80>;
> +       };
> --
> 2.17.1
>
Benjamin Herrenschmidt June 19, 2018, 6:58 a.m. UTC | #2 
On Tue, 2018-06-19 at 16:26 +0930, Joel Stanley wrote:
> On 18 June 2018 at 14:29, Benjamin Herrenschmidt
> <benh@kernel.crashing.org> wrote:
> > Add the device-tree binding definition for the AST2400
> > and AST2500 coprocessor interrupt controller
> > 
> > Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> > ---
> >  .../devicetree/bindings/misc/aspeed,cvic.txt  | 35 +++++++++++++++++++
> >  1 file changed, 35 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/misc/aspeed,cvic.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/misc/aspeed,cvic.txt b/Documentation/devicetree/bindings/misc/aspeed,cvic.txt
> > new file mode 100644
> > index 000000000000..2562e2991e4d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/misc/aspeed,cvic.txt
> 
> Is there a reason you didn't put this in bindings/interrupt-controller?

Well, I don't call it interrupt-controller anymore, it's not an
interrupt controller for the main CPU so I decided to leave it out.

If you (or somebody) has strong feeling about it, I can call it
interrupt-controller again and move it back there :)

> Aside from that this looks good.
> 
> > @@ -0,0 +1,35 @@
> > +* Aspeed AST2400 and AST2500 coprocessor interrupt controller
> > +
> > +This file describes the bindings for the interrupt controller present
> > +in the AST2400 and AST2500 BMC SoCs which provides interrupt to the
> > +ColdFire coprocessor.
> > +
> > +It is not a normal interrupt controller and it would be rather
> > +inconvenient to create an interrupt tree for it as it somewhat shares
> > +some of the same sources as the main ARM interrupt controller but with
> > +different numbers.
> > +
> > +The AST2500 supports a SW generated interrupt
> > +
> > +Required properties:
> > +- reg: address and length of the register for the device.
> > +- compatible: "aspeed,cvic" and one of:
> > +               "aspeed,ast2400-cvic"
> > +             or
> > +               "aspeed,ast2500-cvic"
> > +
> > +- valid-sources: One cell, bitmap of supported sources for the implementation
> > +
> > +Optional properties;
> > +- copro-sw-interrupts: List of interrupt numbers that can be used as
> > +                      SW interrupts from the ARM to the coprocessor.
> > +                      (AST2500 only)
> > +
> > +Example:
> > +
> > +       cvic: copro-interrupt-controller@1e6c2000 {
> > +               compatible = "aspeed,ast2500-cvic";
> > +               valid-sources = <0xffffffff>;
> > +               copro-sw-interrupts = <1>;
> > +               reg = <0x1e6c2000 0x80>;
> > +       };
> > --
> > 2.17.1
> >
Rob Herring June 20, 2018, 7:49 p.m. UTC | #3 
On Mon, Jun 18, 2018 at 02:59:00PM +1000, Benjamin Herrenschmidt wrote:
> Add the device-tree binding definition for the AST2400
> and AST2500 coprocessor interrupt controller
> 
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
>  .../devicetree/bindings/misc/aspeed,cvic.txt  | 35 +++++++++++++++++++
>  1 file changed, 35 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/misc/aspeed,cvic.txt
> 
> diff --git a/Documentation/devicetree/bindings/misc/aspeed,cvic.txt b/Documentation/devicetree/bindings/misc/aspeed,cvic.txt
> new file mode 100644
> index 000000000000..2562e2991e4d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/misc/aspeed,cvic.txt
> @@ -0,0 +1,35 @@
> +* Aspeed AST2400 and AST2500 coprocessor interrupt controller
> +
> +This file describes the bindings for the interrupt controller present
> +in the AST2400 and AST2500 BMC SoCs which provides interrupt to the
> +ColdFire coprocessor.
> +
> +It is not a normal interrupt controller and it would be rather
> +inconvenient to create an interrupt tree for it as it somewhat shares
> +some of the same sources as the main ARM interrupt controller but with
> +different numbers.
> +
> +The AST2500 supports a SW generated interrupt
> +
> +Required properties:
> +- reg: address and length of the register for the device.
> +- compatible: "aspeed,cvic" and one of:
> +		"aspeed,ast2400-cvic"
> +	      or
> +		"aspeed,ast2500-cvic"
> +
> +- valid-sources: One cell, bitmap of supported sources for the implementation

aspeed,valid-sources

This could use a better description. I thought this was which bits to 
use for s/w irq, but then I read the next property...

Alternatively, why can't this be implied by the compatible?

> +
> +Optional properties;
> +- copro-sw-interrupts: List of interrupt numbers that can be used as
> +		       SW interrupts from the ARM to the coprocessor.
> +		       (AST2500 only)
> +
> +Example:
> +
> +	cvic: copro-interrupt-controller@1e6c2000 {
> +		compatible = "aspeed,ast2500-cvic";
> +		valid-sources = <0xffffffff>;
> +		copro-sw-interrupts = <1>;
> +		reg = <0x1e6c2000 0x80>;
> +	};
> -- 
> 2.17.1
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Benjamin Herrenschmidt June 20, 2018, 11:05 p.m. UTC | #4 
On Wed, 2018-06-20 at 13:49 -0600, Rob Herring wrote:
> On Mon, Jun 18, 2018 at 02:59:00PM +1000, Benjamin Herrenschmidt wrote:
> > Add the device-tree binding definition for the AST2400
> > and AST2500 coprocessor interrupt controller
> > 
> > Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> > ---
> >  .../devicetree/bindings/misc/aspeed,cvic.txt  | 35 +++++++++++++++++++
> >  1 file changed, 35 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/misc/aspeed,cvic.txt
> > 
> > diff --git a/Documentation/devicetree/bindings/misc/aspeed,cvic.txt b/Documentation/devicetree/bindings/misc/aspeed,cvic.txt
> > new file mode 100644
> > index 000000000000..2562e2991e4d
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/misc/aspeed,cvic.txt
> > @@ -0,0 +1,35 @@
> > +* Aspeed AST2400 and AST2500 coprocessor interrupt controller
> > +
> > +This file describes the bindings for the interrupt controller present
> > +in the AST2400 and AST2500 BMC SoCs which provides interrupt to the
> > +ColdFire coprocessor.
> > +
> > +It is not a normal interrupt controller and it would be rather
> > +inconvenient to create an interrupt tree for it as it somewhat shares
> > +some of the same sources as the main ARM interrupt controller but with
> > +different numbers.
> > +
> > +The AST2500 supports a SW generated interrupt
> > +
> > +Required properties:
> > +- reg: address and length of the register for the device.
> > +- compatible: "aspeed,cvic" and one of:
> > +		"aspeed,ast2400-cvic"
> > +	      or
> > +		"aspeed,ast2500-cvic"
> > +
> > +- valid-sources: One cell, bitmap of supported sources for the implementation
> 
> aspeed,valid-sources
> 
> This could use a better description. I thought this was which bits to 
> use for s/w irq, but then I read the next property...
> 
> Alternatively, why can't this be implied by the compatible?

It could, I'm happy to drop it, I don't actually use it in SW.

Cheers,
Ben.

> > +
> > +Optional properties;
> > +- copro-sw-interrupts: List of interrupt numbers that can be used as
> > +		       SW interrupts from the ARM to the coprocessor.
> > +		       (AST2500 only)
> > +
> > +Example:
> > +
> > +	cvic: copro-interrupt-controller@1e6c2000 {
> > +		compatible = "aspeed,ast2500-cvic";
> > +		valid-sources = <0xffffffff>;
> > +		copro-sw-interrupts = <1>;
> > +		reg = <0x1e6c2000 0x80>;
> > +	};
> > -- 
> > 2.17.1
> > 
> > 
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/misc/aspeed,cvic.txt b/Documentation/devicetree/bindings/misc/aspeed,cvic.txt
new file mode 100644
index 000000000000..2562e2991e4d
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/aspeed,cvic.txt
@@ -0,0 +1,35 @@ 
+* Aspeed AST2400 and AST2500 coprocessor interrupt controller
+
+This file describes the bindings for the interrupt controller present
+in the AST2400 and AST2500 BMC SoCs which provides interrupt to the
+ColdFire coprocessor.
+
+It is not a normal interrupt controller and it would be rather
+inconvenient to create an interrupt tree for it as it somewhat shares
+some of the same sources as the main ARM interrupt controller but with
+different numbers.
+
+The AST2500 supports a SW generated interrupt
+
+Required properties:
+- reg: address and length of the register for the device.
+- compatible: "aspeed,cvic" and one of:
+		"aspeed,ast2400-cvic"
+	      or
+		"aspeed,ast2500-cvic"
+
+- valid-sources: One cell, bitmap of supported sources for the implementation
+
+Optional properties;
+- copro-sw-interrupts: List of interrupt numbers that can be used as
+		       SW interrupts from the ARM to the coprocessor.
+		       (AST2500 only)
+
+Example:
+
+	cvic: copro-interrupt-controller@1e6c2000 {
+		compatible = "aspeed,ast2500-cvic";
+		valid-sources = <0xffffffff>;
+		copro-sw-interrupts = <1>;
+		reg = <0x1e6c2000 0x80>;
+	};