From patchwork Fri Dec 15 06:24:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 848976 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yygQm3Xvdz9t2M for ; Fri, 15 Dec 2017 17:25:20 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="tPlFAFiZ"; dkim-atps=neutral Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3yygQm26WXzDrnC for ; Fri, 15 Dec 2017 17:25:20 +1100 (AEDT) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="tPlFAFiZ"; dkim-atps=neutral X-Original-To: linux-aspeed@lists.ozlabs.org Delivered-To: linux-aspeed@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:400e:c00::244; helo=mail-pf0-x244.google.com; envelope-from=joel.stan@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="tPlFAFiZ"; dkim-atps=neutral Received: from mail-pf0-x244.google.com (mail-pf0-x244.google.com [IPv6:2607:f8b0:400e:c00::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3yygQj22wGzDrhq for ; Fri, 15 Dec 2017 17:25:17 +1100 (AEDT) Received: by mail-pf0-x244.google.com with SMTP id l24so5491444pfj.6 for ; Thu, 14 Dec 2017 22:25:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=shjmyMylXZHOqCOBFulA4kCeoeosK1EP6VqEWYDZ7gw=; b=tPlFAFiZpghbKd+KqezhLcFJWzW6y7gH6gnBuqYzjYZW0zaIO2QayEzVhdyB3YdzDO BxIcIxMqkkTTV52wAAAMJ6AcmDmjj4dc12shkboASeNTe26AaKCmKBFMbEyUOlITbOYM WLz+aYEAKwLuhEWLWcUlg3yKgwjL0fNz54a+OfXa64MqBg5D7bkfZEtocY+i47TuL9vE J6BXpukENOYk8BhtVpdky0yIDE1atFyh7H4cngt9RyFdW8v+qToruyNiVtH3qybckQgv NoEV43wfILbjQX+5sgjarl4e23EbkQro7hweG1tjSC2xz2rNvyyRqDcNk9K2jkCip+Tj A83g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=shjmyMylXZHOqCOBFulA4kCeoeosK1EP6VqEWYDZ7gw=; b=mUd8nLWqivqWXmjT+wdAoYzdMs/TnEKpeyY5CqIcMN3ojAL2VffCXysfZN6e4Zs28l HS4ELy7odpeJuhHb9nDs+nbQJOO9UuQAHC0zsKP2lScIBYdqG+d7LH2JV28ppv8LGjYg y7OgmcKIJDKfyvUVdDaZdKcw6JQ4L0Pyt1XfnTDfzJpgpCV+D2wC8lmePWcCIP3IQBwk 2YxYaL0hsrVaPu5sg/tlQ3IPPw0b0rfChTTfRGrJToZgDSt+nXp+bDl5R3Eor/qUA5pV A34fgxWetUDVAC9V5mxvfN05WYTjlWNYm4V60KbZ/lsnklOhstrQWf3QMC5Nyzms/cA6 2RDQ== X-Gm-Message-State: AKGB3mLVCneLh+6bvZPXSzmXrzwGDRnIALTot0vhKbjZ94dFkop6AYZO qR6mRH/XFjNuCjr0vb4cm74= X-Google-Smtp-Source: ACJfBotPUpXys867Ewz7fgmoj5QPWY6EIXn0rtkpYEhRXU0AX3eYmFwhm+8iMreVyheTmopwTGMZXg== X-Received: by 10.84.242.76 with SMTP id c12mr12284226pll.445.1513319115235; Thu, 14 Dec 2017 22:25:15 -0800 (PST) Received: from aurora.jms.id.au ([203.0.153.9]) by smtp.gmail.com with ESMTPSA id q9sm12224780pfl.116.2017.12.14.22.25.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 14 Dec 2017 22:25:13 -0800 (PST) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Fri, 15 Dec 2017 16:55:05 +1030 From: Joel Stanley To: Rob Herring , Mark Rutland , Arnd Bergmann , Andrew Jeffery , Patrick Venture , Xo Wang , Lei YU Subject: [PATCH v2 01/19] dt-bindings: clock: Add ASPEED constants Date: Fri, 15 Dec 2017 16:54:25 +1030 Message-Id: <20171215062443.23059-2-joel@jms.id.au> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20171215062443.23059-1-joel@jms.id.au> References: <20171215062443.23059-1-joel@jms.id.au> X-BeenThere: linux-aspeed@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Linux ASPEED SoC development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-aspeed@lists.ozlabs.org, Benjamin Herrenschmidt , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jeremy Kerr Errors-To: linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Linux-aspeed" These will be merged as part of the clock driver. This commit is included so the tree will build without the clock series being applied. Signed-off-by: Joel Stanley Reviewed-by: Rob Herring --- v2: - remove NUM_CLKS define. There's no need for it to be part of ABI --- include/dt-bindings/clock/aspeed-clock.h | 52 ++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 include/dt-bindings/clock/aspeed-clock.h diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h new file mode 100644 index 000000000000..d3558d897a4d --- /dev/null +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +#ifndef DT_BINDINGS_ASPEED_CLOCK_H +#define DT_BINDINGS_ASPEED_CLOCK_H + +#define ASPEED_CLK_GATE_ECLK 0 +#define ASPEED_CLK_GATE_GCLK 1 +#define ASPEED_CLK_GATE_MCLK 2 +#define ASPEED_CLK_GATE_VCLK 3 +#define ASPEED_CLK_GATE_BCLK 4 +#define ASPEED_CLK_GATE_DCLK 5 +#define ASPEED_CLK_GATE_REFCLK 6 +#define ASPEED_CLK_GATE_USBPORT2CLK 7 +#define ASPEED_CLK_GATE_LCLK 8 +#define ASPEED_CLK_GATE_USBUHCICLK 9 +#define ASPEED_CLK_GATE_D1CLK 10 +#define ASPEED_CLK_GATE_YCLK 11 +#define ASPEED_CLK_GATE_USBPORT1CLK 12 +#define ASPEED_CLK_GATE_UART1CLK 13 +#define ASPEED_CLK_GATE_UART2CLK 14 +#define ASPEED_CLK_GATE_UART5CLK 15 +#define ASPEED_CLK_GATE_ESPICLK 16 +#define ASPEED_CLK_GATE_MAC1CLK 17 +#define ASPEED_CLK_GATE_MAC2CLK 18 +#define ASPEED_CLK_GATE_RSACLK 19 +#define ASPEED_CLK_GATE_UART3CLK 20 +#define ASPEED_CLK_GATE_UART4CLK 21 +#define ASPEED_CLK_GATE_SDCLKCLK 22 +#define ASPEED_CLK_GATE_LHCCLK 23 +#define ASPEED_CLK_HPLL 24 +#define ASPEED_CLK_AHB 25 +#define ASPEED_CLK_APB 26 +#define ASPEED_CLK_UART 27 +#define ASPEED_CLK_SDIO 28 +#define ASPEED_CLK_ECLK 29 +#define ASPEED_CLK_ECLK_MUX 30 +#define ASPEED_CLK_LHCLK 31 +#define ASPEED_CLK_MAC 32 +#define ASPEED_CLK_BCLK 33 +#define ASPEED_CLK_MPLL 34 + +#define ASPEED_RESET_XDMA 0 +#define ASPEED_RESET_MCTP 1 +#define ASPEED_RESET_ADC 2 +#define ASPEED_RESET_JTAG_MASTER 3 +#define ASPEED_RESET_MIC 4 +#define ASPEED_RESET_PWM 5 +#define ASPEED_RESET_PCIVGA 6 +#define ASPEED_RESET_I2C 7 +#define ASPEED_RESET_AHB 8 + +#endif