| Message ID | 20220308003745.3930607-1-quic_jaehyoo@quicinc.com |
|---|---|
| Headers | show |
| Series | Fix AST2600 quad mode SPI pinmux settings | expand |
On Tue, Mar 8, 2022 at 1:37 AM Jae Hyun Yoo <quic_jaehyoo@quicinc.com> wrote: > I’m sending this patch series to fix current issues in AST2600 pinmux > settings while enabling quad mode SPI support. Patches 2 & 3 applied to the pinctrl tree. Please funnel the DTS patches through the SoC tree. Yours, Linus Walleij
On Thu, 17 Mar 2022 at 01:11, Linus Walleij <linus.walleij@linaro.org> wrote: > > On Tue, Mar 8, 2022 at 1:37 AM Jae Hyun Yoo <quic_jaehyoo@quicinc.com> wrote: > > > I’m sending this patch series to fix current issues in AST2600 pinmux > > settings while enabling quad mode SPI support. > > Patches 2 & 3 applied to the pinctrl tree. > > Please funnel the DTS patches through the SoC tree. Thanks for jumping on this Linus. We're not sure that this is the correct fix, Andrew is still reviewing (see the comments on patch 3): https://lore.kernel.org/linux-arm-kernel/CACRpkdbFNLLve1-JntNW=eMT9ivZTZHBk-xpwK6w-kE0fczr+g@mail.gmail.com/T/#m2cdf4f8b55427d6040f5c13eb85dd656f3579c48 If you haven't pushed it out then please hold off. If you have, I'll let Andrew jump in and recommend the best course of action. > > Yours, > Linus Walleij
On Thu, Mar 17, 2022 at 2:18 AM Joel Stanley <joel@jms.id.au> wrote: > On Thu, 17 Mar 2022 at 01:11, Linus Walleij <linus.walleij@linaro.org> wrote: > > > > On Tue, Mar 8, 2022 at 1:37 AM Jae Hyun Yoo <quic_jaehyoo@quicinc.com> wrote: > > > > > I’m sending this patch series to fix current issues in AST2600 pinmux > > > settings while enabling quad mode SPI support. > > > > Patches 2 & 3 applied to the pinctrl tree. > > > > Please funnel the DTS patches through the SoC tree. > > Thanks for jumping on this Linus. We're not sure that this is the > correct fix, Andrew is still reviewing (see the comments on patch 3): > > https://lore.kernel.org/linux-arm-kernel/CACRpkdbFNLLve1-JntNW=eMT9ivZTZHBk-xpwK6w-kE0fczr+g@mail.gmail.com/T/#m2cdf4f8b55427d6040f5c13eb85dd656f3579c48 > > If you haven't pushed it out then please hold off. If you have, I'll > let Andrew jump in and recommend the best course of action. I just dropped them again. Yours, Linus Walleij
I’m sending this patch series to fix current issues in AST2600 pinmux settings while enabling quad mode SPI support. FWSPI18 pins are basically 1.8v logic pins that are different from the dedicated FWSPI pins that provide 3.3v logic level, so FWSPI18 pins can’t be grouped with FWSPIDQ2 and FWSPIDQ3, so this series fix the issue. Also, fixes QSPI1 and QSPI2 function settings in AST2600 pinctrl dtsi to make it able to enable quad mode on SPI1 and SPI2 interfaces. With this series, quad mode pinmux can be set like below. FW SPI: &fmc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fwqspi_default>; } SPI1: &spi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi1_default>; } SPI2: &spi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_qspi1_default>; } Please review. Thanks, Jae Jae Hyun Yoo (3): ARM: dts: aspeed-g6: remove FWQSPID group in pinctrl dtsi pinctrl: pinctrl-aspeed-g6: remove FWQSPID group in pinctrl dtsi ARM: dts: aspeed-g6: fix SPI1/SPI2 quad pin group Johnny Huang (2): pinctrl: pinctrl-aspeed-g6: add FWQSPI function-group ARM: dts: aspeed-g6: add FWQSPI group in pinctrl dtsi arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi | 10 +++++----- drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 17 ++++++++--------- 2 files changed, 13 insertions(+), 14 deletions(-)