From patchwork Thu May 5 08:16:47 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Vineet Gupta X-Patchwork-Id: 618870 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2001:1868:205::9]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3r0nnn53Q7z9sD5 for ; Thu, 5 May 2016 18:17:17 +1000 (AEST) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.80.1 #2 (Red Hat Linux)) id 1ayETD-00041N-Sx; Thu, 05 May 2016 08:17:15 +0000 Received: from smtprelay.synopsys.com ([198.182.47.9]) by bombadil.infradead.org with esmtps (Exim 4.80.1 #2 (Red Hat Linux)) id 1ayETB-0003m0-OS for linux-snps-arc@lists.infradead.org; Thu, 05 May 2016 08:17:14 +0000 Received: from us02secmta2.synopsys.com (us02secmta2.synopsys.com [10.12.235.98]) by smtprelay.synopsys.com (Postfix) with ESMTP id 5924B24E13A5; Thu, 5 May 2016 01:16:50 -0700 (PDT) Received: from us02secmta2.internal.synopsys.com (us02secmta2.internal.synopsys.com [127.0.0.1]) by us02secmta2.internal.synopsys.com (Service) with ESMTP id 062A755F15; Thu, 5 May 2016 01:16:50 -0700 (PDT) Received: from mailhost.synopsys.com (mailhost1.synopsys.com [10.12.238.239]) by us02secmta2.internal.synopsys.com (Service) with ESMTP id A025F55F13; Thu, 5 May 2016 01:16:49 -0700 (PDT) Received: from mailhost.synopsys.com (localhost [127.0.0.1]) by mailhost.synopsys.com (Postfix) with ESMTP id 7CC0E800; Thu, 5 May 2016 01:16:49 -0700 (PDT) Received: from us01wehtc1.internal.synopsys.com (us01wehtc1-vip.internal.synopsys.com [10.12.239.236]) by mailhost.synopsys.com (Postfix) with ESMTP id CEF5D7ED; Thu, 5 May 2016 01:16:48 -0700 (PDT) Received: from us01wembx1.internal.synopsys.com ([169.254.1.221]) by us01wehtc1.internal.synopsys.com ([::1]) with mapi id 14.03.0195.001; Thu, 5 May 2016 01:16:48 -0700 From: Vineet Gupta To: Arnd Bergmann , =?iso-8859-2?Q?Horia_Geant=E3?= Subject: Re: [PATCH 1/7] asm-generic/io.h: add io{read,write}64 accessors Thread-Topic: [PATCH 1/7] asm-generic/io.h: add io{read,write}64 accessors Thread-Index: AQHRplVbqY5e73qhRk61hYqRxJqMVw== Date: Thu, 5 May 2016 08:16:47 +0000 Message-ID: References: <1462382179-11889-1-git-send-email-horia.geanta@nxp.com> <16429831.u9JK7qO1GE@wuerfel> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.144.199.106] MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160505_011713_834145_3FFD4386 X-CRM114-Status: GOOD ( 13.02 ) X-Spam-Score: -4.0 (----) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-4.0 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [198.182.47.9 listed in list.dnswl.org] -2.1 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 RCVD_IN_MSPIKE_H4 RBL: Very Good reputation (+4) [198.182.47.9 listed in wl.mailspike.net] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] -0.0 RCVD_IN_MSPIKE_WL Mailspike good senders X-BeenThere: linux-snps-arc@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: Linux on Synopsys ARC Processors List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "linux-arch@vger.kernel.org" , arcml , Herbert Xu , "linux-kernel@vger.kernel.org" , Cristian Stoica , Scott Wood , Noam Camus , "linux-crypto@vger.kernel.org" , Tudor Ambarus , "David S. Miller" , Alexandru Porosanu Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org On Thursday 05 May 2016 04:06 AM, Arnd Bergmann wrote: > On Wednesday 04 May 2016 20:16:19 Horia Geantă wrote: >> @@ -625,6 +645,16 @@ static inline u32 ioread32be(const volatile void __iomem *addr) >> } >> #endif >> >> +#ifdef CONFIG_64BIT >> +#ifndef ioread64be >> +#define ioread64be ioread64be >> +static inline u64 ioread64be(const volatile void __iomem *addr) >> +{ >> + return __be64_to_cpu(__raw_readq(addr)); >> +} >> +#endif >> +#endif /* CONFIG_64BIT */ >> + >> #ifndef iowrite16be >> #define iowrite16be iowrite16be >> static inline void iowrite16be(u16 value, void volatile __iomem *addr) >> @@ -641,6 +671,16 @@ static inline void iowrite32be(u32 value, volatile void __iomem *addr) >> } >> #endif >> >> +#ifdef CONFIG_64BIT >> +#ifndef iowrite64be >> +#define iowrite64be iowrite64be >> +static inline void iowrite64be(u64 value, volatile void __iomem *addr) >> +{ >> + __raw_writeq(__cpu_to_be64(value), addr); >> +} >> +#endif >> +#endif /* CONFIG_64BIT */ >> + >> > I just noticed that these two are both a bit wrong, but they copy the > mistake that already exists in the 16 and 32 bit versions: If an > architecture overrides readq/writeq to have barriers but does not override > ioread64be/iowrite64be, this will lack the barriers and behave differently > from the little-endian version. I think the only affected architecture > is ARC, since ARM and ARM64 both override the big-endian accessors to > have the correct barriers, and all others don't use barriers at all. > > Maybe you can add a patch before this one to replace the 16/32-bit accessors > with ones that do a > > static inline void iowrite32be(u32 value, volatile void __iomem *addr) > { > writel(swab32(value), addr); > } > > This will lead to a double-swap on architectures that don't override it, > but it will work correctly on all architectures without them having > to override the big-endian accessors. Thx for noticing this Arnd and the heads up. Does the patch below look ok to you ? -----------> rom b7e719831c389ab4fa338b2e2e7c0d1ff90dabb0 Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Thu, 5 May 2016 13:32:34 +0530 Subject: [PATCH] ARC: Add missing io barriers to io{read,write}{16,32}be() While reviewing a different change to asm-generic/io.h Arnd spotted that ARC ioread32 and ioread32be both of which come from asm-generic versions are not symmetrical in terms of calling the io barriers. generic ioread32 -> ARC readl() [ has barriers] generic ioread32be -> __be32_to_cpu(__raw_readl()) [ lacks barriers] While generic ioread32be is being remediated to call readl(), that involves a swab32(), causing double swaps on ioread32be() on Big Endian systems. So provide our versions of big endian IO accessors to ensure io barrier calls while also keeping them optimal Suggested-by: Arnd Bergmann Cc: stable@vger.kernel.org [4.2+] Signed-off-by: Vineet Gupta Acked-by: Arnd Bergmann --- arch/arc/include/asm/io.h | 27 ++++++++++++++++++--------- 1 file changed, 18 insertions(+), 9 deletions(-) + /* Change struct page to physical address */ #define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT) @@ -108,15 +126,6 @@ static inline void __raw_writel(u32 w, volatile void __iomem *addr) } -#ifdef CONFIG_ISA_ARCV2 -#include -#define __iormb() rmb() -#define __iowmb() wmb() -#else -#define __iormb() do { } while (0) -#define __iowmb() do { } while (0) -#endif - /* * MMIO can also get buffered/optimized in micro-arch, so barriers needed * Based on ARM model for the typical use case diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h index 17f85c9c73cf..c22b181e8206 100644 --- a/arch/arc/include/asm/io.h +++ b/arch/arc/include/asm/io.h @@ -13,6 +13,15 @@ #include #include +#ifdef CONFIG_ISA_ARCV2 +#include +#define __iormb() rmb() +#define __iowmb() wmb() +#else +#define __iormb() do { } while (0) +#define __iowmb() do { } while (0) +#endif + extern void __iomem *ioremap(phys_addr_t paddr, unsigned long size); extern void __iomem *ioremap_prot(phys_addr_t paddr, unsigned long size, unsigned long flags); @@ -31,6 +40,15 @@ extern void iounmap(const void __iomem *addr); #define ioremap_wc(phy, sz) ioremap(phy, sz) #define ioremap_wt(phy, sz) ioremap(phy, sz) +/* + * io{read,write}{16,32}be() macros + */ +#define ioread16be(p) ({ u16 __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; }) +#define ioread32be(p) ({ u32 __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; }) + +#define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force u16)cpu_to_be16(v), p); }) +#define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force u32)cpu_to_be32(v), p); })