From patchwork Thu Jun 8 15:20:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Noam Camus X-Patchwork-Id: 773325 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3wk8K31q5kz9s7f for ; Fri, 9 Jun 2017 01:21:27 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Zn3Tqt2T"; dkim-atps=neutral DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:MIME-Version:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id:References: In-Reply-To:Message-Id:Date:Subject:To:From:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=tOpMg2YxjVkjfErweNeIXcLdfI2qmXHGtl/sINw7zLY=; b=Zn3Tqt2Tx8OXZwWA7corMIVPZL 2lJpbN/yrmyLZLZx2Q8Ft/unQ3LPU7y5qRU9RNFo2UkHcJUlrUvTXrMXlpWnZ95RCIYGucYgqGPeE XfzReWQ+GmEgufXP/6kq0zcteYKzd7JH9nlrnFERUAPgfePalv9OubDibkqHUX8KFOLaRDUDNQsCr u6rfBGvE4fYeLEJAqiUOPuPq4rNDP9XS+EafgFnnpG7OtGKUSgyeJXZ6F9ixGFUZRsi0iHGQi23WP UNKI4rsX8dlcaknLiSvkY6sm5KgFDLLP2c+TxvqfI7r1rn8Yzig4k3UtlfAgjkIOE9py8K2Wk7eXs KYnRPPmA==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dIzFV-0006o8-R0; Thu, 08 Jun 2017 15:21:25 +0000 Received: from mail-il-dmz.mellanox.com ([193.47.165.129] helo=mellanox.co.il) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1dIzFP-0006go-7M for linux-snps-arc@lists.infradead.org; Thu, 08 Jun 2017 15:21:24 +0000 Received: from Internal Mail-Server by MTLPINE1 (envelope-from noamca@mellanox.com) with ESMTPS (AES256-SHA encrypted); 8 Jun 2017 18:20:53 +0300 Received: from nps20.mtl.labs.mlnx. (l-nps20.mtl.labs.mlnx [10.7.191.20]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id v58FKrah020738; Thu, 8 Jun 2017 18:20:53 +0300 From: Noam Camus To: linux-snps-arc@lists.infradead.org Subject: [PATCH 08/11] ARC: [plat-eznps] Update the init sequence of aux regs per cpu. Date: Thu, 8 Jun 2017 18:20:32 +0300 Message-Id: <1496935235-46507-9-git-send-email-noamca@mellanox.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1496935235-46507-1-git-send-email-noamca@mellanox.com> References: <1496935235-46507-1-git-send-email-noamca@mellanox.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170608_082119_831478_27EDAFFA X-CRM114-Status: UNSURE ( 8.56 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 SPF_PASS SPF: sender matches SPF record -0.0 T_RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -0.0 SPF_HELO_PASS SPF: HELO matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] 0.0 UNPARSEABLE_RELAY Informational: message has unparseable relay lines X-BeenThere: linux-snps-arc@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Linux on Synopsys ARC Processors List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Noam Camus , linux-kernel@vger.kernel.org, Liav Rehana MIME-Version: 1.0 Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org From: Liav Rehana The following commit adds a config that will enable us to distinguish between building the kernel for platforms that have a different set of auxiliary registers for each cpu and platforms that have a shared set of auxiliary registers across every thread in each core. On platforms that implement a different set of auxiliary registers there is a need to initialize them on every cpu and not just the for the first thread of the core. Signed-off-by: Liav Rehana Signed-off-by: Noam Camus --- arch/arc/plat-eznps/Kconfig | 11 +++++++++++ arch/arc/plat-eznps/entry.S | 2 +- 2 files changed, 12 insertions(+), 1 deletions(-) diff --git a/arch/arc/plat-eznps/Kconfig b/arch/arc/plat-eznps/Kconfig index daf749e..812bc29 100644 --- a/arch/arc/plat-eznps/Kconfig +++ b/arch/arc/plat-eznps/Kconfig @@ -44,3 +44,14 @@ config EZNPS_MEM_ERROR for NPS, it handled as an interrupt level 2 (like legacy arc real chip architecture).This configuration will cause the kernel to handle memory error as a machine check exception. + +config EZNPS_SHARED_AUX_REGS + bool "ARC-EZchip Shared Auxiliary Registers Per Core" + depends on ARC_PLAT_EZNPS + default y + help + On the real chip of the NPS, auxiliary registers are shared between + all the cpus of the core, whereas on simulator platform for NPS, + each cpu has a different set of auxiliary registers. Configuration + should be unset if auxiliary registers are not shared between the cpus + of the core, so there will be a need to initialize them per cpu. diff --git a/arch/arc/plat-eznps/entry.S b/arch/arc/plat-eznps/entry.S index 21665ae..4a29c80 100644 --- a/arch/arc/plat-eznps/entry.S +++ b/arch/arc/plat-eznps/entry.S @@ -27,7 +27,7 @@ .align 1024 ; HW requierment for restart first PC ENTRY(res_service) -#ifdef CONFIG_EZNPS_MTM_EXT +#if defined(CONFIG_EZNPS_MTM_EXT) && defined(CONFIG_EZNPS_SHARED_AUX_REGS) ; There is no work for HW thread id != 0 lr r3, [CTOP_AUX_THREAD_ID] cmp r3, 0