Message ID | 1478611259-4477-1-git-send-email-noamca@mellanox.com |
---|---|
State | New |
Headers | show |
Hi Noam, On Tue, 2016-11-08 at 15:20 +0200, Noam Camus wrote: > From: Noam Camus <noamca@mellanox.com> > > For CONFIG_SERIAL_EARLYCON we need 800MHz for NPS SoC > The early console driver uses BASE_BAUD and not using dtb. > > The default of 50MHz is NOT good for NPS SoC. > > Signed-off-by: Noam Camus <noamca@mellanox.com> Could you please provide a changelog (v1 -> v2) so reviewers may have a hint about changes you made if any. Regards, Alexey
> From: Alexey Brodkin [mailto:Alexey.Brodkin@synopsys.com] > Sent: Tuesday, November 8, 2016 4:08 PM >Could you please provide a changelog (v1 -> v2) so reviewers may have a hint about changes you made if any. ... Just fix some typos in log This line somehow was removed from patch while sending (It is at patch head followed by line with ---) Basically in V1 I wrote that default value is good while I meant is NOT good (fixed in V2). Thanks, Noam
Hi Noam, On Tue, 2016-11-08 at 14:13 +0000, Noam Camus wrote: > > > > From: Alexey Brodkin [mailto:Alexey.Brodkin@synopsys.com] > > Sent: Tuesday, November 8, 2016 4:08 PM > > > > > Could you please provide a changelog (v1 -> v2) so reviewers may have a hint about changes you made if any. > ... Just fix some typos in log > This line somehow was removed from patch while sending (It is at patch head followed by line with ---) > Basically in V1 I wrote that default value is good while I meant is NOT good (fixed in V2). Thanks for explanation. IMHO it worth adding that kind of changelog on each next iteration so please keep it in mind next time :) -Alexey
diff --git a/arch/arc/kernel/devtree.c b/arch/arc/kernel/devtree.c index f1e07c2..3b67f53 100644 --- a/arch/arc/kernel/devtree.c +++ b/arch/arc/kernel/devtree.c @@ -31,6 +31,8 @@ static void __init arc_set_early_base_baud(unsigned long dt_root) arc_base_baud = 166666666; /* Fixed 166.6MHz clk (TB10x) */ else if (of_flat_dt_is_compatible(dt_root, "snps,arc-sdp")) arc_base_baud = 33333333; /* Fixed 33MHz clk (AXS10x) */ + else if (of_flat_dt_is_compatible(dt_root, "ezchip,arc-nps")) + arc_base_baud = 800000000; /* Fixed 800MHz clk (NPS) */ else arc_base_baud = 50000000; /* Fixed default 50MHz */ }