@@ -12,10 +12,7 @@
#define NR_CPU_IRQS 32 /* number of interrupt lines of ARC770 CPU */
#define NR_IRQS 128 /* allow some CPU external IRQ handling */
-/* Platform Independent IRQs */
-#ifdef CONFIG_ISA_ARCOMPACT
-#define IPI_IRQ (NR_CPU_IRQS-1) /* dummy to enable SMP build for up hardware */
-#else
+#ifdef CONFIG_ISA_ARCV2
#define IPI_IRQ 19
#endif
@@ -83,9 +83,6 @@ static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq,
{
switch (irq) {
case TIMER0_IRQ:
-#ifdef CONFIG_SMP
- case IPI_IRQ:
-#endif
irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq);
break;
default:
There is no real ARC700 based SMP SoC so remove IPI definition. EZChip's SMP ARC700 is going to use a different intc and IPI provider anyways. Signed-off-by: Vineet Gupta <vgupta@synopsys.com> --- arch/arc/include/asm/irq.h | 5 +---- arch/arc/kernel/intc-compact.c | 3 --- 2 files changed, 1 insertion(+), 7 deletions(-)