@@ -216,6 +216,10 @@ The following keys are defined:
("Zcf doesn't exist on RV64 as it contains no instructions") of
riscv-code-size-reduction.
+ * :c:macro:`RISCV_HWPROBE_EXT_ZCMOP`: The Zcmop May-Be-Operations extension is
+ supported as defined in the RISC-V ISA manual starting from commit
+ c732a4f39a4 ("Zcmop is ratified/1.0").
+
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
information about the selected set of processors.
@@ -65,6 +65,7 @@ struct riscv_hwprobe {
#define RISCV_HWPROBE_EXT_ZCB (1ULL << 39)
#define RISCV_HWPROBE_EXT_ZCD (1ULL << 40)
#define RISCV_HWPROBE_EXT_ZCF (1ULL << 41)
+#define RISCV_HWPROBE_EXT_ZCMOP (1ULL << 42)
#define RISCV_HWPROBE_KEY_CPUPERF_0 5
#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
@@ -115,6 +115,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
EXT_KEY(ZIMOP);
EXT_KEY(ZCA);
EXT_KEY(ZCB);
+ EXT_KEY(ZCMOP);
if (has_vector()) {
EXT_KEY(ZVBB);
Export Zcmop ISA extension through hwprobe. Signed-off-by: Clément Léger <cleger@rivosinc.com> --- Documentation/arch/riscv/hwprobe.rst | 4 ++++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/kernel/sys_hwprobe.c | 1 + 3 files changed, 6 insertions(+)