| Message ID | 20240426100820.14762-14-ajones@ventanamicro.com |
|---|---|
| State | Accepted |
| Headers | show |
| Series | riscv: Apply Zawrs when available | expand |
On Fri, Apr 26, 2024 at 3:38 PM Andrew Jones <ajones@ventanamicro.com> wrote: > > KVM RISC-V allows the Zawrs extension for the Guest/VM, so add it > to the get-reg-list test. > > Signed-off-by: Andrew Jones <ajones@ventanamicro.com> LGTM. Acked-by: Anup Patel <anup@brainfault.org> Thanks, Anup > --- > tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c > index b882b7b9b785..8c4c27bd4b88 100644 > --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c > +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c > @@ -48,6 +48,7 @@ bool filter_reg(__u64 reg) > case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVNAPOT: > case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVPBMT: > case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZACAS: > + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZAWRS: > case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBA: > case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBB: > case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBC: > @@ -413,6 +414,7 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off) > KVM_ISA_EXT_ARR(SVNAPOT), > KVM_ISA_EXT_ARR(SVPBMT), > KVM_ISA_EXT_ARR(ZACAS), > + KVM_ISA_EXT_ARR(ZAWRS), > KVM_ISA_EXT_ARR(ZBA), > KVM_ISA_EXT_ARR(ZBB), > KVM_ISA_EXT_ARR(ZBC), > @@ -936,6 +938,7 @@ KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL); > KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT); > KVM_ISA_EXT_SIMPLE_CONFIG(svpbmt, SVPBMT); > KVM_ISA_EXT_SIMPLE_CONFIG(zacas, ZACAS); > +KVM_ISA_EXT_SIMPLE_CONFIG(zawrs, ZAWRS); > KVM_ISA_EXT_SIMPLE_CONFIG(zba, ZBA); > KVM_ISA_EXT_SIMPLE_CONFIG(zbb, ZBB); > KVM_ISA_EXT_SIMPLE_CONFIG(zbc, ZBC); > @@ -991,6 +994,7 @@ struct vcpu_reg_list *vcpu_configs[] = { > &config_svnapot, > &config_svpbmt, > &config_zacas, > + &config_zawrs, > &config_zba, > &config_zbb, > &config_zbc, > -- > 2.44.0 >
diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index b882b7b9b785..8c4c27bd4b88 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -48,6 +48,7 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVNAPOT: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_SVPBMT: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZACAS: + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZAWRS: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBA: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBB: case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZBC: @@ -413,6 +414,7 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off) KVM_ISA_EXT_ARR(SVNAPOT), KVM_ISA_EXT_ARR(SVPBMT), KVM_ISA_EXT_ARR(ZACAS), + KVM_ISA_EXT_ARR(ZAWRS), KVM_ISA_EXT_ARR(ZBA), KVM_ISA_EXT_ARR(ZBB), KVM_ISA_EXT_ARR(ZBC), @@ -936,6 +938,7 @@ KVM_ISA_EXT_SIMPLE_CONFIG(svinval, SVINVAL); KVM_ISA_EXT_SIMPLE_CONFIG(svnapot, SVNAPOT); KVM_ISA_EXT_SIMPLE_CONFIG(svpbmt, SVPBMT); KVM_ISA_EXT_SIMPLE_CONFIG(zacas, ZACAS); +KVM_ISA_EXT_SIMPLE_CONFIG(zawrs, ZAWRS); KVM_ISA_EXT_SIMPLE_CONFIG(zba, ZBA); KVM_ISA_EXT_SIMPLE_CONFIG(zbb, ZBB); KVM_ISA_EXT_SIMPLE_CONFIG(zbc, ZBC); @@ -991,6 +994,7 @@ struct vcpu_reg_list *vcpu_configs[] = { &config_svnapot, &config_svpbmt, &config_zacas, + &config_zawrs, &config_zba, &config_zbb, &config_zbc,
KVM RISC-V allows the Zawrs extension for the Guest/VM, so add it to the get-reg-list test. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 ++++ 1 file changed, 4 insertions(+)