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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id cv17-20020a17090afd1100b002a02f8d350fsm2628830pjb.53.2024.03.29.02.27.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Mar 2024 02:27:57 -0700 (PDT) From: Max Hsu Date: Fri, 29 Mar 2024 17:26:21 +0800 Subject: [PATCH RFC 05/11] riscv: cpufeature: Add Sdtrig optional CSRs checks MIME-Version: 1.0 Message-Id: <20240329-dev-maxh-lin-452-6-9-v1-5-1534f93b94a7@sifive.com> References: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> In-Reply-To: <20240329-dev-maxh-lin-452-6-9-v1-0-1534f93b94a7@sifive.com> To: Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J. Wysocki" , Pavel Machek , Anup Patel , Atish Patra , Paolo Bonzini , Shuah Khan Cc: Palmer Dabbelt , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Max Hsu X-Mailer: b4 0.13.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240329_092800_075145_D26873EF X-CRM114-Status: GOOD ( 19.27 ) X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "desiato.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Sdtrig extension introduce two optional CSRs [hcontext/scontext], that will be storing PID/Guest OS ID for the debug feature. The availability of these two CSRs will be determined by DTS and Smstateen extension [h/s]stateen0 CSR bit 57. Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:102f listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: kvm-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "kvm-riscv" Errors-To: kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Sdtrig extension introduce two optional CSRs [hcontext/scontext], that will be storing PID/Guest OS ID for the debug feature. The availability of these two CSRs will be determined by DTS and Smstateen extension [h/s]stateen0 CSR bit 57. If all CPUs hcontext/scontext checks are satisfied, it will enable the use_hcontext/use_scontext static branch. Signed-off-by: Max Hsu --- arch/riscv/include/asm/switch_to.h | 6 ++ arch/riscv/kernel/cpufeature.c | 161 +++++++++++++++++++++++++++++++++++++ 2 files changed, 167 insertions(+) diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h index 7efdb0584d47..07432550ed54 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -69,6 +69,12 @@ static __always_inline bool has_fpu(void) { return false; } #define __switch_to_fpu(__prev, __next) do { } while (0) #endif +DECLARE_STATIC_KEY_FALSE(use_scontext); +static __always_inline bool has_scontext(void) +{ + return static_branch_likely(&use_scontext); +} + extern struct task_struct *__switch_to(struct task_struct *, struct task_struct *); diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 080c06b76f53..44ff84b920af 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -35,6 +35,19 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; /* Per-cpu ISA extensions. */ struct riscv_isainfo hart_isa[NR_CPUS]; +atomic_t hcontext_disable; +atomic_t scontext_disable; + +DEFINE_STATIC_KEY_FALSE_RO(use_hcontext); +EXPORT_SYMBOL(use_hcontext); + +DEFINE_STATIC_KEY_FALSE_RO(use_scontext); +EXPORT_SYMBOL(use_scontext); + +/* Record the maximum number that the hcontext CSR allowed to hold */ +atomic_long_t hcontext_id_share; +EXPORT_SYMBOL(hcontext_id_share); + /** * riscv_isa_extension_base() - Get base extension word * @@ -719,6 +732,154 @@ unsigned long riscv_get_elf_hwcap(void) return hwcap; } +static void __init sdtrig_percpu_csrs_check(void *data) +{ + struct device_node *node; + struct device_node *debug_node; + struct device_node *trigger_module; + + unsigned int cpu = smp_processor_id(); + + /* + * Expect every cpu node has the [h/s]context-present property + * otherwise, jump to sdtrig_csrs_disable_all to disable all access to + * [h/s]context CSRs + */ + node = of_cpu_device_node_get(cpu); + if (!node) + goto sdtrig_csrs_disable_all; + + debug_node = of_get_compatible_child(node, "riscv,debug-v1.0.0"); + of_node_put(node); + + if (!debug_node) + goto sdtrig_csrs_disable_all; + + trigger_module = of_get_child_by_name(debug_node, "trigger-module"); + of_node_put(debug_node); + + if (!trigger_module) + goto sdtrig_csrs_disable_all; + + if (!(IS_ENABLED(CONFIG_KVM) && + of_property_read_bool(trigger_module, "hcontext-present"))) + atomic_inc(&hcontext_disable); + + if (!of_property_read_bool(trigger_module, "scontext-present")) + atomic_inc(&scontext_disable); + + of_node_put(trigger_module); + + /* + * Before access to hcontext/scontext CSRs, if the smstateen + * extension is present, the accessibility will be controlled + * by the hstateen0[H]/sstateen0 CSRs. + */ + if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SMSTATEEN)) { + u64 hstateen_bit, sstateen_bit; + + if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_h)) { +#if __riscv_xlen > 32 + csr_set(CSR_HSTATEEN0, SMSTATEEN0_HSCONTEXT); + hstateen_bit = csr_read(CSR_HSTATEEN0); +#else + csr_set(CSR_HSTATEEN0H, SMSTATEEN0_HSCONTEXT >> 32); + hstateen_bit = csr_read(CSR_HSTATEEN0H) << 32; +#endif + if (!(hstateen_bit & SMSTATEEN0_HSCONTEXT)) + goto sdtrig_csrs_disable_all; + + } else { + if (IS_ENABLED(CONFIG_KVM)) + atomic_inc(&hcontext_disable); + + /* + * In RV32, the smstateen extension doesn't provide + * high 32 bits of sstateen0 CSR which represent + * accessibility for scontext CSR; + * The decision is left on whether the dts has the + * property to access the scontext CSR. + */ +#if __riscv_xlen > 32 + csr_set(CSR_SSTATEEN0, SMSTATEEN0_HSCONTEXT); + sstateen_bit = csr_read(CSR_SSTATEEN0); + + if (!(sstateen_bit & SMSTATEEN0_HSCONTEXT)) + atomic_inc(&scontext_disable); +#endif + } + } + + /* + * The code can only access hcontext/scontext CSRs if: + * The cpu dts node have [h/s]context-present; + * If Smstateen extension is presented, then the accessibility bit + * toward hcontext/scontext CSRs is enabled; Or the Smstateen extension + * isn't available, thus the access won't be blocked by it. + * + * With writing 1 to the every bit of these CSRs, we retrieve the + * maximum bits that is available on the CSRs. and decide + * whether it's suit for its context recording operation. + */ + if (IS_ENABLED(CONFIG_KVM) && + !atomic_read(&hcontext_disable)) { + unsigned long hcontext_available_bits = 0; + + csr_write(CSR_HCONTEXT, -1UL); + hcontext_available_bits = csr_swap(CSR_HCONTEXT, hcontext_available_bits); + + /* hcontext CSR is required by at least 1 bit */ + if (hcontext_available_bits) + atomic_long_and(hcontext_available_bits, &hcontext_id_share); + else + atomic_inc(&hcontext_disable); + } + + if (!atomic_read(&scontext_disable)) { + unsigned long scontext_available_bits = 0; + + csr_write(CSR_SCONTEXT, -1UL); + scontext_available_bits = csr_swap(CSR_SCONTEXT, scontext_available_bits); + + /* scontext CSR is required by at least the sizeof pid_t */ + if (scontext_available_bits < ((1UL << (sizeof(pid_t) << 3)) - 1)) + atomic_inc(&scontext_disable); + } + + return; + +sdtrig_csrs_disable_all: + if (IS_ENABLED(CONFIG_KVM)) + atomic_inc(&hcontext_disable); + + atomic_inc(&scontext_disable); +} + +static int __init sdtrig_enable_csrs_fill(void) +{ + if (__riscv_isa_extension_available(NULL, RISCV_ISA_EXT_SDTRIG)) { + atomic_long_set(&hcontext_id_share, -1UL); + + /* check every CPUs sdtrig extension optional CSRs */ + sdtrig_percpu_csrs_check(NULL); + smp_call_function(sdtrig_percpu_csrs_check, NULL, 1); + + if (IS_ENABLED(CONFIG_KVM) && + !atomic_read(&hcontext_disable)) { + pr_info("riscv-sdtrig: Writing 'GuestOS ID' to hcontext CSR is enabled\n"); + static_branch_enable(&use_hcontext); + } + + if (!atomic_read(&scontext_disable)) { + pr_info("riscv-sdtrig: Writing 'PID' to scontext CSR is enabled\n"); + static_branch_enable(&use_scontext); + } + } + return 0; +} + +arch_initcall(sdtrig_enable_csrs_fill); + void riscv_user_isa_enable(void) { if (riscv_cpu_has_extension_unlikely(smp_processor_id(), RISCV_ISA_EXT_ZICBOZ))