[kvmtool,04/10] riscv: Add Zba and Zbs extension support

Message ID	20231128145628.413414-5-apatel@ventanamicro.com
State	Accepted
Headers	show Return-Path: <kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org> From: Anup Patel <apatel@ventanamicro.com> To: Will Deacon <will@kernel.org>, julien.thierry.kdev@gmail.com, maz@kernel.org Cc: Paolo Bonzini <pbonzini@redhat.com>, Atish Patra <atishp@atishpatra.org>, Andrew Jones <ajones@ventanamicro.com>, Anup Patel <anup@brainfault.org>, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Anup Patel <apatel@ventanamicro.com> Subject: [kvmtool PATCH 04/10] riscv: Add Zba and Zbs extension support Date: Tue, 28 Nov 2023 20:26:22 +0530 Message-Id: <20231128145628.413414-5-apatel@ventanamicro.com> In-Reply-To: <20231128145628.413414-1-apatel@ventanamicro.com> References: <20231128145628.413414-1-apatel@ventanamicro.com> MIME-Version: 1.0 preview: When the Zba and Zbs extension is available expose it to the guest via device tree so that guest can use it. Signed-off-by: Anup Patel <apatel@ventanamicro.com> --- riscv/fdt.c \| 2 ++ riscv/include/kvm/kvm-config-arch.h \| 6 ++++++ 2 files changed, 8 insertions(+) Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:629 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "kvm-riscv" <kvm-riscv-bounces@lists.infradead.org> Errors-To: kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org
Series	SBI debug console and few ISA extensions \| expand [kvmtool,00/10] SBI debug console and few ISA extensions [kvmtool,01/10] Sync-up header with Linux-6.7-rc3 for KVM RISC-V [kvmtool,02/10] riscv: Improve warning in generate_cpu_nodes() [kvmtool,03/10] riscv: Make CPU_ISA_MAX_LEN depend upon isa_info_arr array size [kvmtool,04/10] riscv: Add Zba and Zbs extension support [kvmtool,05/10] riscv: Add Zicntr and Zihpm extension support [kvmtool,06/10] riscv: Add Zicsr and Zifencei extension support [kvmtool,07/10] riscv: Add Smstateen extension support [kvmtool,08/10] riscv: Add Zicond extension support [kvmtool,09/10] riscv: Set mmu-type DT property based on satp_mode ONE_REG interface [kvmtool,10/10] riscv: Handle SBI DBCN calls from Guest/VM

Message ID

20231128145628.413414-5-apatel@ventanamicro.com

State

Accepted

Headers

From: Anup Patel <apatel@ventanamicro.com>
To: Will Deacon <will@kernel.org>,
	julien.thierry.kdev@gmail.com,
	maz@kernel.org
Cc: Paolo Bonzini <pbonzini@redhat.com>,
	Atish Patra <atishp@atishpatra.org>,
	Andrew Jones <ajones@ventanamicro.com>,
	Anup Patel <anup@brainfault.org>,
	kvm@vger.kernel.org,
	kvm-riscv@lists.infradead.org,
	Anup Patel <apatel@ventanamicro.com>
Subject: [kvmtool PATCH 04/10] riscv: Add Zba and Zbs extension support
Date: Tue, 28 Nov 2023 20:26:22 +0530
Message-Id: <20231128145628.413414-5-apatel@ventanamicro.com>
In-Reply-To: <20231128145628.413414-1-apatel@ventanamicro.com>
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Series

SBI debug console and few ISA extensions | expand

Commit Message

Anup Patel Nov. 28, 2023, 2:56 p.m. UTC

When the Zba and Zbs extension is available expose it to the guest
via device tree so that guest can use it.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 riscv/fdt.c                         | 2 ++
 riscv/include/kvm/kvm-config-arch.h | 6 ++++++
 2 files changed, 8 insertions(+)

diff --git a/riscv/fdt.c b/riscv/fdt.c
index 230d1f8..cfe4678 100644
--- a/riscv/fdt.c
+++ b/riscv/fdt.c
@@ -21,7 +21,9 @@  struct isa_ext_info isa_info_arr[] = {
 	{"svinval", KVM_RISCV_ISA_EXT_SVINVAL},
 	{"svnapot", KVM_RISCV_ISA_EXT_SVNAPOT},
 	{"svpbmt", KVM_RISCV_ISA_EXT_SVPBMT},
+	{"zba", KVM_RISCV_ISA_EXT_ZBA},
 	{"zbb", KVM_RISCV_ISA_EXT_ZBB},
+	{"zbs", KVM_RISCV_ISA_EXT_ZBS},
 	{"zicbom", KVM_RISCV_ISA_EXT_ZICBOM},
 	{"zicboz", KVM_RISCV_ISA_EXT_ZICBOZ},
 	{"zihintpause", KVM_RISCV_ISA_EXT_ZIHINTPAUSE},
diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h
index 863baea..978037a 100644
--- a/riscv/include/kvm/kvm-config-arch.h
+++ b/riscv/include/kvm/kvm-config-arch.h
@@ -40,9 +40,15 @@  struct kvm_config_arch {
 	OPT_BOOLEAN('\0', "disable-svpbmt",				\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_SVPBMT],	\
 		    "Disable Svpbmt Extension"),			\
+	OPT_BOOLEAN('\0', "disable-zba",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBA],	\
+		    "Disable Zba Extension"),				\
 	OPT_BOOLEAN('\0', "disable-zbb",				\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBB],	\
 		    "Disable Zbb Extension"),				\
+	OPT_BOOLEAN('\0', "disable-zbs",				\
+		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZBS],	\
+		    "Disable Zbs Extension"),				\
 	OPT_BOOLEAN('\0', "disable-zicbom",				\
 		    &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZICBOM],	\
 		    "Disable Zicbom Extension"),			\

[kvmtool,04/10] riscv: Add Zba and Zbs extension support

Commit Message

Patch