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Thu, 06 Jul 2023 10:38:41 -0700 (PDT) From: Anup Patel To: Will Deacon , julien.thierry.kdev@gmail.com, maz@kernel.org Cc: Paolo Bonzini , Atish Patra , Andrew Jones , Anup Patel , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, Anup Patel Subject: [kvmtool PATCH v3 3/8] riscv: Allow disabling SBI extensions for Guest Date: Thu, 6 Jul 2023 23:07:59 +0530 Message-Id: <20230706173804.1237348-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230706173804.1237348-1-apatel@ventanamicro.com> References: <20230706173804.1237348-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230706_103842_894758_05CBF239 X-CRM114-Status: GOOD ( 12.79 ) X-Spam-Score: -0.2 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: We add "--disable-sbi-" options to disable various SBI extensions visible to the Guest. This allows users to disable deprecated/redundant SBI extensions. Signed-off-by: Anup Patel --- riscv/include/kvm/kvm-config-arch.h | 30 ++++++++++++++++++++++++++++- riscv/include/kvm/kvm-cpu-arch.h | 19 +++++++++++------- riscv/kvm-cpu.c [...] Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:d31 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain X-BeenThere: kvm-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "kvm-riscv" Errors-To: kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org We add "--disable-sbi-" options to disable various SBI extensions visible to the Guest. This allows users to disable deprecated/redundant SBI extensions. Signed-off-by: Anup Patel --- riscv/include/kvm/kvm-config-arch.h | 30 ++++++++++++++++++++++++++++- riscv/include/kvm/kvm-cpu-arch.h | 19 +++++++++++------- riscv/kvm-cpu.c | 19 +++++++++++++++++- 3 files changed, 59 insertions(+), 9 deletions(-) diff --git a/riscv/include/kvm/kvm-config-arch.h b/riscv/include/kvm/kvm-config-arch.h index e64e3ca..56676e3 100644 --- a/riscv/include/kvm/kvm-config-arch.h +++ b/riscv/include/kvm/kvm-config-arch.h @@ -9,6 +9,7 @@ struct kvm_config_arch { u64 custom_marchid; u64 custom_mimpid; bool ext_disabled[KVM_RISCV_ISA_EXT_MAX]; + bool sbi_ext_disabled[KVM_RISCV_SBI_EXT_MAX]; }; #define OPT_ARCH_RUN(pfx, cfg) \ @@ -38,6 +39,33 @@ struct kvm_config_arch { "Disable Zicbom Extension"), \ OPT_BOOLEAN('\0', "disable-zihintpause", \ &(cfg)->ext_disabled[KVM_RISCV_ISA_EXT_ZIHINTPAUSE],\ - "Disable Zihintpause Extension"), + "Disable Zihintpause Extension"), \ + OPT_BOOLEAN('\0', "disable-sbi-legacy", \ + &(cfg)->sbi_ext_disabled[KVM_RISCV_SBI_EXT_V01], \ + "Disable SBI Legacy Extensions"), \ + OPT_BOOLEAN('\0', "disable-sbi-time", \ + &(cfg)->sbi_ext_disabled[KVM_RISCV_SBI_EXT_TIME], \ + "Disable SBI Time Extension"), \ + OPT_BOOLEAN('\0', "disable-sbi-ipi", \ + &(cfg)->sbi_ext_disabled[KVM_RISCV_SBI_EXT_IPI], \ + "Disable SBI IPI Extension"), \ + OPT_BOOLEAN('\0', "disable-sbi-rfence", \ + &(cfg)->sbi_ext_disabled[KVM_RISCV_SBI_EXT_RFENCE], \ + "Disable SBI RFence Extension"), \ + OPT_BOOLEAN('\0', "disable-sbi-srst", \ + &(cfg)->sbi_ext_disabled[KVM_RISCV_SBI_EXT_SRST], \ + "Disable SBI SRST Extension"), \ + OPT_BOOLEAN('\0', "disable-sbi-hsm", \ + &(cfg)->sbi_ext_disabled[KVM_RISCV_SBI_EXT_HSM], \ + "Disable SBI HSM Extension"), \ + OPT_BOOLEAN('\0', "disable-sbi-pmu", \ + &(cfg)->sbi_ext_disabled[KVM_RISCV_SBI_EXT_PMU], \ + "Disable SBI PMU Extension"), \ + OPT_BOOLEAN('\0', "disable-sbi-experimental", \ + &(cfg)->sbi_ext_disabled[KVM_RISCV_SBI_EXT_EXPERIMENTAL],\ + "Disable SBI Experimental Extensions"), \ + OPT_BOOLEAN('\0', "disable-sbi-vendor", \ + &(cfg)->sbi_ext_disabled[KVM_RISCV_SBI_EXT_VENDOR], \ + "Disable SBI Vendor Extensions"), #endif /* KVM__KVM_CONFIG_ARCH_H */ diff --git a/riscv/include/kvm/kvm-cpu-arch.h b/riscv/include/kvm/kvm-cpu-arch.h index e014839..1e9a7b0 100644 --- a/riscv/include/kvm/kvm-cpu-arch.h +++ b/riscv/include/kvm/kvm-cpu-arch.h @@ -7,9 +7,10 @@ #include "kvm/kvm.h" -static inline __u64 __kvm_reg_id(__u64 type, __u64 idx, __u64 size) +static inline __u64 __kvm_reg_id(__u64 type, __u64 subtype, + __u64 idx, __u64 size) { - return KVM_REG_RISCV | type | idx | size; + return KVM_REG_RISCV | type | subtype | idx | size; } #if __riscv_xlen == 64 @@ -18,25 +19,29 @@ static inline __u64 __kvm_reg_id(__u64 type, __u64 idx, __u64 size) #define KVM_REG_SIZE_ULONG KVM_REG_SIZE_U32 #endif -#define RISCV_CONFIG_REG(name) __kvm_reg_id(KVM_REG_RISCV_CONFIG, \ +#define RISCV_CONFIG_REG(name) __kvm_reg_id(KVM_REG_RISCV_CONFIG, 0, \ KVM_REG_RISCV_CONFIG_REG(name), \ KVM_REG_SIZE_ULONG) -#define RISCV_ISA_EXT_REG(id) __kvm_reg_id(KVM_REG_RISCV_ISA_EXT, \ +#define RISCV_ISA_EXT_REG(id) __kvm_reg_id(KVM_REG_RISCV_ISA_EXT, 0, \ id, KVM_REG_SIZE_ULONG) -#define RISCV_CORE_REG(name) __kvm_reg_id(KVM_REG_RISCV_CORE, \ +#define RISCV_CORE_REG(name) __kvm_reg_id(KVM_REG_RISCV_CORE, 0, \ KVM_REG_RISCV_CORE_REG(name), \ KVM_REG_SIZE_ULONG) -#define RISCV_CSR_REG(name) __kvm_reg_id(KVM_REG_RISCV_CSR, \ +#define RISCV_CSR_REG(name) __kvm_reg_id(KVM_REG_RISCV_CSR, 0, \ KVM_REG_RISCV_CSR_REG(name), \ KVM_REG_SIZE_ULONG) -#define RISCV_TIMER_REG(name) __kvm_reg_id(KVM_REG_RISCV_TIMER, \ +#define RISCV_TIMER_REG(name) __kvm_reg_id(KVM_REG_RISCV_TIMER, 0, \ KVM_REG_RISCV_TIMER_REG(name), \ KVM_REG_SIZE_U64) +#define RISCV_SBI_EXT_REG(subtype, id) \ + __kvm_reg_id(KVM_REG_RISCV_SBI_EXT, subtype, \ + id, KVM_REG_SIZE_ULONG) + struct kvm_cpu { pthread_t thread; diff --git a/riscv/kvm-cpu.c b/riscv/kvm-cpu.c index 89122b4..540baec 100644 --- a/riscv/kvm-cpu.c +++ b/riscv/kvm-cpu.c @@ -23,7 +23,8 @@ struct kvm_cpu *kvm_cpu__arch_init(struct kvm *kvm, unsigned long cpu_id) struct kvm_cpu *vcpu; u64 timebase = 0; unsigned long isa = 0, id = 0; - int coalesced_offset, mmap_size; + unsigned long masks[KVM_REG_RISCV_SBI_MULTI_REG_LAST + 1] = { 0 }; + int i, coalesced_offset, mmap_size; struct kvm_one_reg reg; vcpu = calloc(1, sizeof(struct kvm_cpu)); @@ -88,6 +89,22 @@ struct kvm_cpu *kvm_cpu__arch_init(struct kvm *kvm, unsigned long cpu_id) die("KVM_SET_ONE_REG failed (config.mimpid)"); } + for (i = 0; i < KVM_RISCV_SBI_EXT_MAX; i++) { + if (!kvm->cfg.arch.sbi_ext_disabled[i]) + continue; + masks[KVM_REG_RISCV_SBI_MULTI_REG(i)] |= + KVM_REG_RISCV_SBI_MULTI_MASK(i); + } + for (i = 0; i <= KVM_REG_RISCV_SBI_MULTI_REG_LAST; i++) { + if (!masks[i]) + continue; + + reg.id = RISCV_SBI_EXT_REG(KVM_REG_RISCV_SBI_MULTI_DIS, i); + reg.addr = (unsigned long)&masks[i]; + if (ioctl(vcpu->vcpu_fd, KVM_SET_ONE_REG, ®) < 0) + die("KVM_SET_ONE_REG failed (sbi_ext %d)", i); + } + /* Populate the vcpu structure. */ vcpu->kvm = kvm; vcpu->cpu_id = cpu_id;