[v5,08/13] riscv: module: Add ADD16 and SUB16 rela types

Message ID	20230128172856.3814-9-jszhang@kernel.org
State	Accepted
Headers	show Return-Path: <kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org> From: Jisheng Zhang <jszhang@kernel.org> To: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Albert Ou <aou@eecs.berkeley.edu>, Anup Patel <anup@brainfault.org>, Atish Patra <atishp@atishpatra.org>, Heiko Stuebner <heiko@sntech.de>, Andrew Jones <ajones@ventanamicro.com>, Conor Dooley <conor.dooley@microchip.com> Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org Subject: [PATCH v5 08/13] riscv: module: Add ADD16 and SUB16 rela types Date: Sun, 29 Jan 2023 01:28:51 +0800 Message-Id: <20230128172856.3814-9-jszhang@kernel.org> In-Reply-To: <20230128172856.3814-1-jszhang@kernel.org> References: <20230128172856.3814-1-jszhang@kernel.org> MIME-Version: 1.0 preview: From: Andrew Jones <ajones@ventanamicro.com> To prepare for 16-bit relocation types to be emitted in alternatives add support for ADD16 and SUB16. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> --- arch/riscv/kernel/module.c \| 16 ++++++++++++++++ 1 file changed, 16 insertions(+) Content analysis details: (-2.7 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at https://www.dnswl.org/, medium trust [2604:1380:4641:c500:0:0:0:1 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain -0.2 DKIMWL_WL_HIGH DKIMwl.org - High trust sender Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "kvm-riscv" <kvm-riscv-bounces@lists.infradead.org> Errors-To: kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org
Series	riscv: improve boot time isa extensions handling \| expand [v5,00/13] riscv: improve boot time isa extensions handling [v5,01/13] riscv: move riscv_noncoherent_supported() out of ZICBOM probe [v5,02/13] riscv: cpufeature: detect RISCV_ALTERNATIVES_EARLY_BOOT earlier [v5,03/13] riscv: hwcap: make ISA extension ids can be used in asm [v5,04/13] riscv: cpufeature: extend riscv_cpufeature_patch_func to all ISA extensions [v5,05/13] riscv: introduce riscv_has_extension_[un]likely() [v5,06/13] riscv: fpu: switch has_fpu() to riscv_has_extension_likely() [v5,07/13] riscv: module: move find_section to module.h [v5,08/13] riscv: module: Add ADD16 and SUB16 rela types [v5,09/13] riscv: switch to relative alternative entries [v5,10/13] riscv: alternative: patch alternatives in the vDSO [v5,11/13] riscv: cpu_relax: switch to riscv_has_extension_likely() [v5,12/13] riscv: KVM: Switch has_svinval() to riscv_has_extension_unlikely() [v5,13/13] riscv: remove riscv_isa_ext_keys[] array and related usage

Message ID

20230128172856.3814-9-jszhang@kernel.org

State

Accepted

Headers

From: Jisheng Zhang <jszhang@kernel.org>
To: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Anup Patel <anup@brainfault.org>,
	Atish Patra <atishp@atishpatra.org>,
	Heiko Stuebner <heiko@sntech.de>,
	Andrew Jones <ajones@ventanamicro.com>,
	Conor Dooley <conor.dooley@microchip.com>
Cc: linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	kvm@vger.kernel.org,
	kvm-riscv@lists.infradead.org
Subject: [PATCH v5 08/13] riscv: module: Add ADD16 and SUB16 rela types
Date: Sun, 29 Jan 2023 01:28:51 +0800
Message-Id: <20230128172856.3814-9-jszhang@kernel.org>
In-Reply-To: <20230128172856.3814-1-jszhang@kernel.org>
References: <20230128172856.3814-1-jszhang@kernel.org>
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Series

riscv: improve boot time isa extensions handling | expand

Commit Message

Jisheng Zhang Jan. 28, 2023, 5:28 p.m. UTC

From: Andrew Jones <ajones@ventanamicro.com>

To prepare for 16-bit relocation types to be emitted in alternatives
add support for ADD16 and SUB16.

Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/kernel/module.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/riscv/kernel/module.c b/arch/riscv/kernel/module.c
index 76f4b9c2ec5b..7c651d55fcbd 100644
--- a/arch/riscv/kernel/module.c
+++ b/arch/riscv/kernel/module.c
@@ -268,6 +268,13 @@  static int apply_r_riscv_align_rela(struct module *me, u32 *location,
 	return -EINVAL;
 }
 
+static int apply_r_riscv_add16_rela(struct module *me, u32 *location,
+				    Elf_Addr v)
+{
+	*(u16 *)location += (u16)v;
+	return 0;
+}
+
 static int apply_r_riscv_add32_rela(struct module *me, u32 *location,
 				    Elf_Addr v)
 {
@@ -282,6 +289,13 @@  static int apply_r_riscv_add64_rela(struct module *me, u32 *location,
 	return 0;
 }
 
+static int apply_r_riscv_sub16_rela(struct module *me, u32 *location,
+				    Elf_Addr v)
+{
+	*(u16 *)location -= (u16)v;
+	return 0;
+}
+
 static int apply_r_riscv_sub32_rela(struct module *me, u32 *location,
 				    Elf_Addr v)
 {
@@ -315,8 +329,10 @@  static int (*reloc_handlers_rela[]) (struct module *me, u32 *location,
 	[R_RISCV_CALL]			= apply_r_riscv_call_rela,
 	[R_RISCV_RELAX]			= apply_r_riscv_relax_rela,
 	[R_RISCV_ALIGN]			= apply_r_riscv_align_rela,
+	[R_RISCV_ADD16]			= apply_r_riscv_add16_rela,
 	[R_RISCV_ADD32]			= apply_r_riscv_add32_rela,
 	[R_RISCV_ADD64]			= apply_r_riscv_add64_rela,
+	[R_RISCV_SUB16]			= apply_r_riscv_sub16_rela,
 	[R_RISCV_SUB32]			= apply_r_riscv_sub32_rela,
 	[R_RISCV_SUB64]			= apply_r_riscv_sub64_rela,
 };

[v5,08/13] riscv: module: Add ADD16 and SUB16 rela types

Commit Message

Patch