| Message ID | 20230112140304.1830648-3-apatel@ventanamicro.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | RISC-V KVM virtualize AIA CSRs | expand |
On Thu, Jan 12, 2023 at 07:32:59PM +0530, Anup Patel wrote: > We have two extension names for AIA ISA support: Smaia (M-mode AIA CSRs) > and Ssaia (S-mode AIA CSRs). > > We extend the ISA string parsing to detect Smaia and Ssaia extensions. > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > --- > arch/riscv/include/asm/hwcap.h | 8 ++++++++ > arch/riscv/kernel/cpu.c | 2 ++ > arch/riscv/kernel/cpufeature.c | 2 ++ > 3 files changed, 12 insertions(+) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 86328e3acb02..c649e85ed7bb 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -59,10 +59,18 @@ enum riscv_isa_ext_id { > RISCV_ISA_EXT_ZIHINTPAUSE, > RISCV_ISA_EXT_SSTC, > RISCV_ISA_EXT_SVINVAL, > + RISCV_ISA_EXT_SSAIA, > + RISCV_ISA_EXT_SMAIA, These will change a couple different ways due other other patches in flight, but let's put the pair in alphabetical order now so they get moved together that way. > RISCV_ISA_EXT_ID_MAX > }; > static_assert(RISCV_ISA_EXT_ID_MAX <= RISCV_ISA_EXT_MAX); > > +#ifdef CONFIG_RISCV_M_MODE > +#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA > +#else > +#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA > +#endif This isn't used in this patch, so should probably be introduced in a later patch when it is. > + > /* > * This enum represents the logical ID for each RISC-V ISA extension static > * keys. We can use static key to optimize code path if some ISA extensions > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > index 1b9a5a66e55a..a215ec929160 100644 > --- a/arch/riscv/kernel/cpu.c > +++ b/arch/riscv/kernel/cpu.c > @@ -162,6 +162,8 @@ arch_initcall(riscv_cpuinfo_init); > * extensions by an underscore. > */ > static struct riscv_isa_ext_data isa_ext_arr[] = { > + __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), > + __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), > __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), > __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 93e45560af30..3c5b51f519d5 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -228,6 +228,8 @@ void __init riscv_fill_hwcap(void) > SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); > SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); > SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL); > + SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA); > + SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA); > } > #undef SET_ISA_EXT_MAP > } > -- > 2.34.1 > Otherwise, Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Thanks, drew
On Thu, Jan 26, 2023 at 9:32 PM Andrew Jones <ajones@ventanamicro.com> wrote: > > On Thu, Jan 12, 2023 at 07:32:59PM +0530, Anup Patel wrote: > > We have two extension names for AIA ISA support: Smaia (M-mode AIA CSRs) > > and Ssaia (S-mode AIA CSRs). > > > > We extend the ISA string parsing to detect Smaia and Ssaia extensions. > > > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > > --- > > arch/riscv/include/asm/hwcap.h | 8 ++++++++ > > arch/riscv/kernel/cpu.c | 2 ++ > > arch/riscv/kernel/cpufeature.c | 2 ++ > > 3 files changed, 12 insertions(+) > > > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > > index 86328e3acb02..c649e85ed7bb 100644 > > --- a/arch/riscv/include/asm/hwcap.h > > +++ b/arch/riscv/include/asm/hwcap.h > > @@ -59,10 +59,18 @@ enum riscv_isa_ext_id { > > RISCV_ISA_EXT_ZIHINTPAUSE, > > RISCV_ISA_EXT_SSTC, > > RISCV_ISA_EXT_SVINVAL, > > + RISCV_ISA_EXT_SSAIA, > > + RISCV_ISA_EXT_SMAIA, > > These will change a couple different ways due other other patches in > flight, but let's put the pair in alphabetical order now so they get > moved together that way. Okay, I will update. > > > RISCV_ISA_EXT_ID_MAX > > }; > > static_assert(RISCV_ISA_EXT_ID_MAX <= RISCV_ISA_EXT_MAX); > > > > +#ifdef CONFIG_RISCV_M_MODE > > +#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA > > +#else > > +#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA > > +#endif > > This isn't used in this patch, so should probably be introduced in a later > patch when it is. Okay, I will move this to the patch where it is used. > > > + > > /* > > * This enum represents the logical ID for each RISC-V ISA extension static > > * keys. We can use static key to optimize code path if some ISA extensions > > diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c > > index 1b9a5a66e55a..a215ec929160 100644 > > --- a/arch/riscv/kernel/cpu.c > > +++ b/arch/riscv/kernel/cpu.c > > @@ -162,6 +162,8 @@ arch_initcall(riscv_cpuinfo_init); > > * extensions by an underscore. > > */ > > static struct riscv_isa_ext_data isa_ext_arr[] = { > > + __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), > > + __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), > > __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), > > __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), > > __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > > index 93e45560af30..3c5b51f519d5 100644 > > --- a/arch/riscv/kernel/cpufeature.c > > +++ b/arch/riscv/kernel/cpufeature.c > > @@ -228,6 +228,8 @@ void __init riscv_fill_hwcap(void) > > SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); > > SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); > > SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL); > > + SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA); > > + SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA); > > } > > #undef SET_ISA_EXT_MAP > > } > > -- > > 2.34.1 > > > > Otherwise, > > Reviewed-by: Andrew Jones <ajones@ventanamicro.com> > Thanks, Anup
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 86328e3acb02..c649e85ed7bb 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -59,10 +59,18 @@ enum riscv_isa_ext_id { RISCV_ISA_EXT_ZIHINTPAUSE, RISCV_ISA_EXT_SSTC, RISCV_ISA_EXT_SVINVAL, + RISCV_ISA_EXT_SSAIA, + RISCV_ISA_EXT_SMAIA, RISCV_ISA_EXT_ID_MAX }; static_assert(RISCV_ISA_EXT_ID_MAX <= RISCV_ISA_EXT_MAX); +#ifdef CONFIG_RISCV_M_MODE +#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SMAIA +#else +#define RISCV_ISA_EXT_SxAIA RISCV_ISA_EXT_SSAIA +#endif + /* * This enum represents the logical ID for each RISC-V ISA extension static * keys. We can use static key to optimize code path if some ISA extensions diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 1b9a5a66e55a..a215ec929160 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -162,6 +162,8 @@ arch_initcall(riscv_cpuinfo_init); * extensions by an underscore. */ static struct riscv_isa_ext_data isa_ext_arr[] = { + __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), + __RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 93e45560af30..3c5b51f519d5 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -228,6 +228,8 @@ void __init riscv_fill_hwcap(void) SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL); + SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA); + SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA); } #undef SET_ISA_EXT_MAP }
We have two extension names for AIA ISA support: Smaia (M-mode AIA CSRs) and Ssaia (S-mode AIA CSRs). We extend the ISA string parsing to detect Smaia and Ssaia extensions. Signed-off-by: Anup Patel <apatel@ventanamicro.com> --- arch/riscv/include/asm/hwcap.h | 8 ++++++++ arch/riscv/kernel/cpu.c | 2 ++ arch/riscv/kernel/cpufeature.c | 2 ++ 3 files changed, 12 insertions(+)