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Mon, 18 Jul 2022 10:05:45 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Anup Patel , Atish Patra , Guo Ren , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Will Deacon Subject: [RFC 2/9] RISC-V: Define a helper function to return counter width Date: Mon, 18 Jul 2022 10:01:58 -0700 Message-Id: <20220718170205.2972215-3-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220718170205.2972215-1-atishp@rivosinc.com> References: <20220718170205.2972215-1-atishp@rivosinc.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220718_100547_145988_A69D7CFD X-CRM114-Status: GOOD ( 15.00 ) X-Spam-Score: 0.0 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: The virtual hardware counters need to have the same width as the logical hardware counters for simplicity. However, there shouldn't be mapping between virtual hardware counters and logical hardware co [...] Content analysis details: (0.0 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:102b listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: kvm-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "kvm-riscv" Errors-To: kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org The virtual hardware counters need to have the same width as the logical hardware counters for simplicity. However, there shouldn't be mapping between virtual hardware counters and logical hardware counters. As we don't support hetergeneous harts or counters with different width as of now, the implementation relies on the counter width of the first available programmable counter. Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_sbi.c | 25 +++++++++++++++++++++++++ include/linux/perf/riscv_pmu.h | 1 + 2 files changed, 26 insertions(+) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 1723af68ffa1..5d0eef3ef136 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -250,6 +250,31 @@ static bool pmu_sbi_ctr_is_fw(int cidx) return (info->type == SBI_PMU_CTR_TYPE_FW) ? true : false; } +/* + * Returns the counter width of a programmable counter + * As we don't support heterneous CPUs yet, it is okay to just + * return the counter width of the first programmable counter. + */ +int riscv_pmu_sbi_hpmc_width(void) +{ + int i; + union sbi_pmu_ctr_info *info; + + if (!rvpmu) + return -EINVAL; + + for (i = 0; i < rvpmu->num_counters; i++) { + info = &pmu_ctr_list[i]; + if (!info) + continue; + if (info->type == SBI_PMU_CTR_TYPE_HW) + return info->width; + } + + return 0; +} +EXPORT_SYMBOL(riscv_pmu_sbi_hpmc_width); + static int pmu_sbi_ctr_get_idx(struct perf_event *event) { struct hw_perf_event *hwc = &event->hw; diff --git a/include/linux/perf/riscv_pmu.h b/include/linux/perf/riscv_pmu.h index fc47167e000c..6fee211c27b5 100644 --- a/include/linux/perf/riscv_pmu.h +++ b/include/linux/perf/riscv_pmu.h @@ -72,6 +72,7 @@ static inline void riscv_pmu_legacy_skip_init(void) {}; struct riscv_pmu *riscv_pmu_alloc(void); #ifdef CONFIG_RISCV_PMU_SBI int riscv_pmu_sbi_get_num_hw_ctrs(void); +int riscv_pmu_sbi_hpmc_width(void); #endif #endif /* CONFIG_RISCV_PMU */