[v2,2/7] RISC-V: KVM: Add Sv57x4 mode support for G-stage

Message ID	20220420112450.155624-3-apatel@ventanamicro.com
State	Accepted
Headers	show Return-Path: <kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org> From: Anup Patel <apatel@ventanamicro.com> To: Paolo Bonzini <pbonzini@redhat.com>, Atish Patra <atishp@atishpatra.org> Cc: Palmer Dabbelt <palmer@dabbelt.com>, Paul Walmsley <paul.walmsley@sifive.com>, Alistair Francis <Alistair.Francis@wdc.com>, Anup Patel <anup@brainfault.org>, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Anup Patel <apatel@ventanamicro.com> Subject: [PATCH v2 2/7] RISC-V: KVM: Add Sv57x4 mode support for G-stage Date: Wed, 20 Apr 2022 16:54:45 +0530 Message-Id: <20220420112450.155624-3-apatel@ventanamicro.com> In-Reply-To: <20220420112450.155624-1-apatel@ventanamicro.com> References: <20220420112450.155624-1-apatel@ventanamicro.com> MIME-Version: 1.0 preview: Latest QEMU supports G-stage Sv57x4 mode so this patch extends KVM RISC-V G-stage handling to detect and use Sv57x4 mode when available. Signed-off-by: Anup Patel <apatel@ventanamicro.com> --- arch/riscv/include/asm/csr.h \| 1 + arch/riscv/kvm/main.c \| 3 +++ arch/riscv/kvm/mmu.c \| 11 ++++++++++- 3 files changed, 14 insertions(+), 1 dele [...] Content analysis details: (-0.2 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:52c listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID_AU Message has a valid DKIM or DK signature from author's domain -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid -0.1 DKIM_VALID_EF Message has a valid DKIM or DK signature from envelope-from domain Precedence: list Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "kvm-riscv" <kvm-riscv-bounces@lists.infradead.org> Errors-To: kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org
Series	KVM RISC-V Sv57x4 support and HFENCE improvements \| expand [v2,0/7] KVM RISC-V Sv57x4 support and HFENCE improvements [v2,1/7] RISC-V: KVM: Use G-stage name for hypervisor page table [v2,2/7] RISC-V: KVM: Add Sv57x4 mode support for G-stage [v2,3/7] RISC-V: KVM: Treat SBI HFENCE calls as NOPs [v2,4/7] RISC-V: KVM: Introduce range based local HFENCE functions [v2,5/7] RISC-V: KVM: Reduce KVM_MAX_VCPUS value [v2,6/7] RISC-V: KVM: Add remote HFENCE functions based on VCPU requests [v2,7/7] RISC-V: KVM: Cleanup stale TLB entries when host CPU changes

Message ID

20220420112450.155624-3-apatel@ventanamicro.com

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Accepted

Headers

From: Anup Patel <apatel@ventanamicro.com>
To: Paolo Bonzini <pbonzini@redhat.com>,
	Atish Patra <atishp@atishpatra.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
 Paul Walmsley <paul.walmsley@sifive.com>,
 Alistair Francis <Alistair.Francis@wdc.com>,
 Anup Patel <anup@brainfault.org>, kvm@vger.kernel.org,
 kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
 linux-kernel@vger.kernel.org, Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH v2 2/7] RISC-V: KVM: Add Sv57x4 mode support for G-stage
Date: Wed, 20 Apr 2022 16:54:45 +0530
Message-Id: <20220420112450.155624-3-apatel@ventanamicro.com>
In-Reply-To: <20220420112450.155624-1-apatel@ventanamicro.com>
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Series

KVM RISC-V Sv57x4 support and HFENCE improvements | expand

Commit Message

Anup Patel April 20, 2022, 11:24 a.m. UTC

Latest QEMU supports G-stage Sv57x4 mode so this patch extends KVM
RISC-V G-stage handling to detect and use Sv57x4 mode when available.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 arch/riscv/include/asm/csr.h |  1 +
 arch/riscv/kvm/main.c        |  3 +++
 arch/riscv/kvm/mmu.c         | 11 ++++++++++-
 3 files changed, 14 insertions(+), 1 deletion(-)

Comments

Atish Patra May 4, 2022, 2:14 a.m. UTC | #1

On Wed, Apr 20, 2022 at 4:25 AM Anup Patel <apatel@ventanamicro.com> wrote:
>
> Latest QEMU supports G-stage Sv57x4 mode so this patch extends KVM
> RISC-V G-stage handling to detect and use Sv57x4 mode when available.
>
> Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> ---
>  arch/riscv/include/asm/csr.h |  1 +
>  arch/riscv/kvm/main.c        |  3 +++
>  arch/riscv/kvm/mmu.c         | 11 ++++++++++-
>  3 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> index e935f27b10fd..cc40521e438b 100644
> --- a/arch/riscv/include/asm/csr.h
> +++ b/arch/riscv/include/asm/csr.h
> @@ -117,6 +117,7 @@
>  #define HGATP_MODE_SV32X4      _AC(1, UL)
>  #define HGATP_MODE_SV39X4      _AC(8, UL)
>  #define HGATP_MODE_SV48X4      _AC(9, UL)
> +#define HGATP_MODE_SV57X4      _AC(10, UL)
>
>  #define HGATP32_MODE_SHIFT     31
>  #define HGATP32_VMID_SHIFT     22
> diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c
> index c374dad82eee..1549205fe5fe 100644
> --- a/arch/riscv/kvm/main.c
> +++ b/arch/riscv/kvm/main.c
> @@ -105,6 +105,9 @@ int kvm_arch_init(void *opaque)
>         case HGATP_MODE_SV48X4:
>                 str = "Sv48x4";
>                 break;
> +       case HGATP_MODE_SV57X4:
> +               str = "Sv57x4";
> +               break;
>         default:
>                 return -ENODEV;
>         }
> diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c
> index dc0520792e31..8823eb32dcde 100644
> --- a/arch/riscv/kvm/mmu.c
> +++ b/arch/riscv/kvm/mmu.c
> @@ -751,14 +751,23 @@ void kvm_riscv_gstage_update_hgatp(struct kvm_vcpu *vcpu)
>  void kvm_riscv_gstage_mode_detect(void)
>  {
>  #ifdef CONFIG_64BIT
> +       /* Try Sv57x4 G-stage mode */
> +       csr_write(CSR_HGATP, HGATP_MODE_SV57X4 << HGATP_MODE_SHIFT);
> +       if ((csr_read(CSR_HGATP) >> HGATP_MODE_SHIFT) == HGATP_MODE_SV57X4) {
> +               gstage_mode = (HGATP_MODE_SV57X4 << HGATP_MODE_SHIFT);
> +               gstage_pgd_levels = 5;
> +               goto skip_sv48x4_test;
> +       }
> +
>         /* Try Sv48x4 G-stage mode */
>         csr_write(CSR_HGATP, HGATP_MODE_SV48X4 << HGATP_MODE_SHIFT);
>         if ((csr_read(CSR_HGATP) >> HGATP_MODE_SHIFT) == HGATP_MODE_SV48X4) {
>                 gstage_mode = (HGATP_MODE_SV48X4 << HGATP_MODE_SHIFT);
>                 gstage_pgd_levels = 4;
>         }
> -       csr_write(CSR_HGATP, 0);
> +skip_sv48x4_test:
>
> +       csr_write(CSR_HGATP, 0);
>         __kvm_riscv_hfence_gvma_all();
>  #endif
>  }
> --
> 2.25.1
>

Reviewed-by: Atish Patra <atishp@rivosinc.com>

Anup Patel May 9, 2022, 5:31 a.m. UTC | #2

On Wed, May 4, 2022 at 7:44 AM Atish Patra <atishp@atishpatra.org> wrote:
>
> On Wed, Apr 20, 2022 at 4:25 AM Anup Patel <apatel@ventanamicro.com> wrote:
> >
> > Latest QEMU supports G-stage Sv57x4 mode so this patch extends KVM
> > RISC-V G-stage handling to detect and use Sv57x4 mode when available.
> >
> > Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> > ---
> >  arch/riscv/include/asm/csr.h |  1 +
> >  arch/riscv/kvm/main.c        |  3 +++
> >  arch/riscv/kvm/mmu.c         | 11 ++++++++++-
> >  3 files changed, 14 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> > index e935f27b10fd..cc40521e438b 100644
> > --- a/arch/riscv/include/asm/csr.h
> > +++ b/arch/riscv/include/asm/csr.h
> > @@ -117,6 +117,7 @@
> >  #define HGATP_MODE_SV32X4      _AC(1, UL)
> >  #define HGATP_MODE_SV39X4      _AC(8, UL)
> >  #define HGATP_MODE_SV48X4      _AC(9, UL)
> > +#define HGATP_MODE_SV57X4      _AC(10, UL)
> >
> >  #define HGATP32_MODE_SHIFT     31
> >  #define HGATP32_VMID_SHIFT     22
> > diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c
> > index c374dad82eee..1549205fe5fe 100644
> > --- a/arch/riscv/kvm/main.c
> > +++ b/arch/riscv/kvm/main.c
> > @@ -105,6 +105,9 @@ int kvm_arch_init(void *opaque)
> >         case HGATP_MODE_SV48X4:
> >                 str = "Sv48x4";
> >                 break;
> > +       case HGATP_MODE_SV57X4:
> > +               str = "Sv57x4";
> > +               break;
> >         default:
> >                 return -ENODEV;
> >         }
> > diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c
> > index dc0520792e31..8823eb32dcde 100644
> > --- a/arch/riscv/kvm/mmu.c
> > +++ b/arch/riscv/kvm/mmu.c
> > @@ -751,14 +751,23 @@ void kvm_riscv_gstage_update_hgatp(struct kvm_vcpu *vcpu)
> >  void kvm_riscv_gstage_mode_detect(void)
> >  {
> >  #ifdef CONFIG_64BIT
> > +       /* Try Sv57x4 G-stage mode */
> > +       csr_write(CSR_HGATP, HGATP_MODE_SV57X4 << HGATP_MODE_SHIFT);
> > +       if ((csr_read(CSR_HGATP) >> HGATP_MODE_SHIFT) == HGATP_MODE_SV57X4) {
> > +               gstage_mode = (HGATP_MODE_SV57X4 << HGATP_MODE_SHIFT);
> > +               gstage_pgd_levels = 5;
> > +               goto skip_sv48x4_test;
> > +       }
> > +
> >         /* Try Sv48x4 G-stage mode */
> >         csr_write(CSR_HGATP, HGATP_MODE_SV48X4 << HGATP_MODE_SHIFT);
> >         if ((csr_read(CSR_HGATP) >> HGATP_MODE_SHIFT) == HGATP_MODE_SV48X4) {
> >                 gstage_mode = (HGATP_MODE_SV48X4 << HGATP_MODE_SHIFT);
> >                 gstage_pgd_levels = 4;
> >         }
> > -       csr_write(CSR_HGATP, 0);
> > +skip_sv48x4_test:
> >
> > +       csr_write(CSR_HGATP, 0);
> >         __kvm_riscv_hfence_gvma_all();
> >  #endif
> >  }
> > --
> > 2.25.1
> >
>
> Reviewed-by: Atish Patra <atishp@rivosinc.com>

Queued this patch for 5.19

Thanks,
Anup

>
> --
> Regards,
> Atish

diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index e935f27b10fd..cc40521e438b 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -117,6 +117,7 @@ 
 #define HGATP_MODE_SV32X4	_AC(1, UL)
 #define HGATP_MODE_SV39X4	_AC(8, UL)
 #define HGATP_MODE_SV48X4	_AC(9, UL)
+#define HGATP_MODE_SV57X4	_AC(10, UL)
 
 #define HGATP32_MODE_SHIFT	31
 #define HGATP32_VMID_SHIFT	22
diff --git a/arch/riscv/kvm/main.c b/arch/riscv/kvm/main.c
index c374dad82eee..1549205fe5fe 100644
--- a/arch/riscv/kvm/main.c
+++ b/arch/riscv/kvm/main.c
@@ -105,6 +105,9 @@  int kvm_arch_init(void *opaque)
 	case HGATP_MODE_SV48X4:
 		str = "Sv48x4";
 		break;
+	case HGATP_MODE_SV57X4:
+		str = "Sv57x4";
+		break;
 	default:
 		return -ENODEV;
 	}
diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c
index dc0520792e31..8823eb32dcde 100644
--- a/arch/riscv/kvm/mmu.c
+++ b/arch/riscv/kvm/mmu.c
@@ -751,14 +751,23 @@  void kvm_riscv_gstage_update_hgatp(struct kvm_vcpu *vcpu)
 void kvm_riscv_gstage_mode_detect(void)
 {
 #ifdef CONFIG_64BIT
+	/* Try Sv57x4 G-stage mode */
+	csr_write(CSR_HGATP, HGATP_MODE_SV57X4 << HGATP_MODE_SHIFT);
+	if ((csr_read(CSR_HGATP) >> HGATP_MODE_SHIFT) == HGATP_MODE_SV57X4) {
+		gstage_mode = (HGATP_MODE_SV57X4 << HGATP_MODE_SHIFT);
+		gstage_pgd_levels = 5;
+		goto skip_sv48x4_test;
+	}
+
 	/* Try Sv48x4 G-stage mode */
 	csr_write(CSR_HGATP, HGATP_MODE_SV48X4 << HGATP_MODE_SHIFT);
 	if ((csr_read(CSR_HGATP) >> HGATP_MODE_SHIFT) == HGATP_MODE_SV48X4) {
 		gstage_mode = (HGATP_MODE_SV48X4 << HGATP_MODE_SHIFT);
 		gstage_pgd_levels = 4;
 	}
-	csr_write(CSR_HGATP, 0);
+skip_sv48x4_test:
 
+	csr_write(CSR_HGATP, 0);
 	__kvm_riscv_hfence_gvma_all();
 #endif
 }

[v2,2/7] RISC-V: KVM: Add Sv57x4 mode support for G-stage

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