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[0/4] riscv: Introduce support for defining instructions

Message ID 20220819140250.3892995-1-ajones@ventanamicro.com
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Series riscv: Introduce support for defining instructions | expand

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Andrew Jones Aug. 19, 2022, 2:02 p.m. UTC 
When compiling with toolchains that haven't yet been taught about
new instructions we need to encode them ourselves. This series
creates a new file where support for instruction definitions can
evolve. For starters the file is initiated with a macro for R-type
encodings. The series then applies the R-type encoding macro to all
instances of hard coded instruction definitions in KVM.

Not only should using instruction encoding macros improve readability
and maintainability of code, but we should also gain potential for
more optimized code after compilation as the compiler will have control
over the input and output registers used, which may provide more
opportunities for inlining.

I grepped for other places we may want to use these macros and the
only place I found was ALT_CMO_OP(), but I didn't dare touch it :-)
I do suggest we apply this to the Svinal support [1] as we won't
want to frustrate the compiler's inlining efforts with hard coded
register selection.

[1] https://lore.kernel.org/linux-riscv/20220812042921.14508-1-mchitale@ventanamicro.com/

Andrew Jones (4):
  riscv: Add X register names to gpr-nums
  riscv: Introduce support for defining instructions
  riscv: KVM: Apply insn-def to hfence encodings
  riscv: KVM: Apply insn-def to hlv encodings

 arch/riscv/Kconfig                |   3 +
 arch/riscv/include/asm/gpr-num.h  |   8 ++
 arch/riscv/include/asm/insn-def.h | 104 ++++++++++++++++++++++++++
 arch/riscv/kvm/tlb.c              | 117 ++++--------------------------
 arch/riscv/kvm/vcpu_exit.c        |  29 ++------
 5 files changed, 133 insertions(+), 128 deletions(-)
 create mode 100644 arch/riscv/include/asm/insn-def.h