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Mon, 18 Jul 2022 10:05:42 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Atish Patra , Albert Ou , Anup Patel , Atish Patra , Guo Ren , kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Will Deacon Subject: [RFC 0/9] KVM perf support Date: Mon, 18 Jul 2022 10:01:56 -0700 Message-Id: <20220718170205.2972215-1-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220718_100545_639529_29752699 X-CRM114-Status: GOOD ( 12.12 ) X-Spam-Score: 0.0 (/) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: This series extends perf support for KVM. The KVM implementation relies on the SBI PMU extension and trap n emulation of hpmcounter CSRs. The KVM implementation exposes the virtual counters to the gue [...] Content analysis details: (0.0 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no trust [2607:f8b0:4864:20:0:0:0:429 listed in] [list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record -0.1 DKIM_VALID Message has at least one valid DKIM or DK signature 0.1 DKIM_SIGNED Message has a DKIM or DK signature, not necessarily valid X-BeenThere: kvm-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "kvm-riscv" Errors-To: kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org This series extends perf support for KVM. The KVM implementation relies on the SBI PMU extension and trap n emulation of hpmcounter CSRs. The KVM implementation exposes the virtual counters to the guest and internally manage the counters using kernel perf counters. This series doesn't support the counter overflow as the Sscofpmf extension doesn't allow trap & emulation mechanism of scountovf CSR yet. The required changes to allow that are being under discussions. Supporting overflow interrupt also requires AIA support which is not frozen either. This series can be found at github[1] as well. It depends Anup's CSR emulation framework[1] series. perf stat works in kvm guests with this series. Here is example of running perf stat in a guest running in KVM. =========================================================================== / # /host/apps/perf stat -e instructions -e cycles -e r8000000000000005 \ > -e r8000000000000006 -e r8000000000000007 -e r8000000000000008 \ > -e r800000000000000a perf bench sched messaging -g 5 -l 15 # Running 'sched/messaging' benchmark: # 20 sender and receiver processes per group # 5 groups == 200 processes run Total time: 5.210 [sec] Performance counter stats for 'perf bench sched messaging -g 5 -l 15': 37209585734 instructions # 1.00 insn per cycle 37177435570 cycles 2740 r8000000000000005 3727 r8000000000000006 3655 r8000000000000007 10 r8000000000000008 0 r800000000000000a 5.863014800 seconds time elapsed 0.569373000 seconds user 10.771533000 seconds sys [1] https://github.com/atishp04/linux/tree/kvm_perf_rfc [2] https://lkml.org/lkml/2022/6/15/389 Atish Patra (9): RISC-V: Define a helper function to probe number of hardware counters RISC-V: Define a helper function to return counter width RISC-V: KVM: Define a probe function for SBI extension data structures RISC-V: KVM: Improve privilege mode filtering for perf RISC-V: KVM: Add skeleton support for perf RISC-V: KVM: Add SBI PMU extension support RISC-V: KVM: Implement trap & emulate for hpmcounters RISC-V: KVM: Implement perf support RISC-V: KVM: Implement firmware events arch/riscv/include/asm/kvm_host.h | 3 + arch/riscv/include/asm/kvm_vcpu_pmu.h | 102 +++++ arch/riscv/include/asm/kvm_vcpu_sbi.h | 3 + arch/riscv/include/asm/sbi.h | 2 +- arch/riscv/kvm/Makefile | 1 + arch/riscv/kvm/main.c | 3 +- arch/riscv/kvm/tlb.c | 6 +- arch/riscv/kvm/vcpu.c | 5 + arch/riscv/kvm/vcpu_insn.c | 4 +- arch/riscv/kvm/vcpu_pmu.c | 517 ++++++++++++++++++++++++++ arch/riscv/kvm/vcpu_sbi.c | 11 + arch/riscv/kvm/vcpu_sbi_base.c | 13 +- arch/riscv/kvm/vcpu_sbi_pmu.c | 81 ++++ arch/riscv/kvm/vcpu_sbi_replace.c | 7 + drivers/perf/riscv_pmu_sbi.c | 75 +++- include/linux/perf/riscv_pmu.h | 7 + 16 files changed, 823 insertions(+), 17 deletions(-) create mode 100644 arch/riscv/include/asm/kvm_vcpu_pmu.h create mode 100644 arch/riscv/kvm/vcpu_pmu.c create mode 100644 arch/riscv/kvm/vcpu_sbi_pmu.c --- 2.25.1