diff mbox

[5/6] KVM: PPC: Book3S HV: Access XICS in BE

Message ID 53A0312D.8090607@suse.de
State New, archived
Headers show

Commit Message

Alexander Graf June 17, 2014, 12:14 p.m. UTC 
On 17.06.14 14:13, Paul Mackerras wrote:
> On Tue, Jun 17, 2014 at 12:22:32PM +0200, Alexander Graf wrote:
>> Eh, no. What we do is we read (good on BE, byte reversed) into r0. Then we
>> swab32() from r0 to r3 on LE, mr from r0 to r3 on BE.
>>
>> r3 gets truncated along the way.
>>
>> The reason we maintain r0 as wrong-endian is that we write it back using the
>> cache inhibited stwcix instruction:
>>
>>>         stwcix  r0, r6, r7              /* EOI it */
>> So during the lifetime of r0 as XIRR it's always byte-reversed on LE. That's
>> why we store it using STWX_BE into hstate, because that's the time when we
>> actually swab32() it for further interpretation.
> So the STWX_BE is more like a be32_to_cpu than a cpu_to_be32, which is
> what the name STWX_BE would suggest.  Sounds like it at least deserves
> a comment, or (as you suggest) rearrange the register usage so a
> normal store works.

Yes, I have this now:


 From a94a66437ec714ec5650f6d8fec050a33e4477ca Mon Sep 17 00:00:00 2001
From: Alexander Graf <agraf@suse.de>
Date: Wed, 11 Jun 2014 10:37:52 +0200
Subject: [PATCH] KVM: PPC: Book3S HV: Access XICS in BE

On the exit path from the guest we check what type of interrupt we received
if we received one. This means we're doing hardware access to the XICS 
interrupt
controller.

However, when running on a little endian system, this access is byte 
reversed.

So let's make sure to swizzle the bytes back again and virtually make XICS
accesses big endian.

Signed-off-by: Alexander Graf <agraf@suse.de>

---

v1 -> v2:

   - Make code easier to follow


Alex

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diff mbox

Patch

diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S 
b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
index 1a2f471..9829e18 100644
--- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S
+++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S
@@ -36,6 +36,13 @@ 
  #define NAPPING_CEDE    1
  #define NAPPING_NOVCPU    2

+.macro bswap32 regd, regs
+    srwi    \regd,\regs,24
+    rlwimi    \regd,\regs,24,16,23
+    rlwimi    \regd,\regs,8,8,15
+    rlwimi    \regd,\regs,24,0,7
+.endm
+
  /*
   * Call kvmppc_hv_entry in real mode.
   * Must be called with interrupts hard-disabled.
@@ -2325,7 +2332,12 @@  kvmppc_read_intr:
      cmpdi    r6, 0
      beq-    1f
      lwzcix    r0, r6, r7
-    rlwinm.    r3, r0, 0, 0xffffff
+#ifdef __LITTLE_ENDIAN__
+    bswap32    r4, r0
+#else
+    mr    r4, r0
+#endif
+    rlwinm.    r3, r4, 0, 0xffffff
      sync
      beq    1f            /* if nothing pending in the ICP */

@@ -2360,7 +2372,7 @@  kvmppc_read_intr:
  42:    /* It's not an IPI and it's for the host, stash it in the PACA
       * before exit, it will be picked up by the host ICP driver
       */
-    stw    r0, HSTATE_SAVED_XIRR(r13)
+    stw    r4, HSTATE_SAVED_XIRR(r13)
      li    r3, 1
      b    1b