| Message ID | 20211004160049.1338837-3-npiggin@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | KVM: PPC: Book3S HV P9: entry/exit optimisations | expand |
Nicholas Piggin <npiggin@gmail.com> writes: > The TIDR SPR only exists on POWER9. Avoid accessing it when the > feature bit for it is not set. Not related to this patch, but how does this work with compat mode? A P9 compat mode guest would get an invalid instruction when trying to access this SPR? > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> > --- > arch/powerpc/kvm/book3s_hv.c | 12 ++++++++---- > arch/powerpc/xmon/xmon.c | 10 ++++++++-- > 2 files changed, 16 insertions(+), 6 deletions(-) > > diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c > index 2acb1c96cfaf..f4a779fffd18 100644 > --- a/arch/powerpc/kvm/book3s_hv.c > +++ b/arch/powerpc/kvm/book3s_hv.c > @@ -3767,7 +3767,8 @@ static void load_spr_state(struct kvm_vcpu *vcpu) > mtspr(SPRN_EBBHR, vcpu->arch.ebbhr); > mtspr(SPRN_EBBRR, vcpu->arch.ebbrr); > mtspr(SPRN_BESCR, vcpu->arch.bescr); > - mtspr(SPRN_TIDR, vcpu->arch.tid); > + if (cpu_has_feature(CPU_FTR_P9_TIDR)) > + mtspr(SPRN_TIDR, vcpu->arch.tid); > mtspr(SPRN_AMR, vcpu->arch.amr); > mtspr(SPRN_UAMOR, vcpu->arch.uamor); > > @@ -3793,7 +3794,8 @@ static void store_spr_state(struct kvm_vcpu *vcpu) > vcpu->arch.ebbhr = mfspr(SPRN_EBBHR); > vcpu->arch.ebbrr = mfspr(SPRN_EBBRR); > vcpu->arch.bescr = mfspr(SPRN_BESCR); > - vcpu->arch.tid = mfspr(SPRN_TIDR); > + if (cpu_has_feature(CPU_FTR_P9_TIDR)) > + vcpu->arch.tid = mfspr(SPRN_TIDR); > vcpu->arch.amr = mfspr(SPRN_AMR); > vcpu->arch.uamor = mfspr(SPRN_UAMOR); > vcpu->arch.dscr = mfspr(SPRN_DSCR); > @@ -3813,7 +3815,8 @@ struct p9_host_os_sprs { > static void save_p9_host_os_sprs(struct p9_host_os_sprs *host_os_sprs) > { > host_os_sprs->dscr = mfspr(SPRN_DSCR); > - host_os_sprs->tidr = mfspr(SPRN_TIDR); > + if (cpu_has_feature(CPU_FTR_P9_TIDR)) > + host_os_sprs->tidr = mfspr(SPRN_TIDR); > host_os_sprs->iamr = mfspr(SPRN_IAMR); > host_os_sprs->amr = mfspr(SPRN_AMR); > host_os_sprs->fscr = mfspr(SPRN_FSCR); > @@ -3827,7 +3830,8 @@ static void restore_p9_host_os_sprs(struct kvm_vcpu *vcpu, > mtspr(SPRN_UAMOR, 0); > > mtspr(SPRN_DSCR, host_os_sprs->dscr); > - mtspr(SPRN_TIDR, host_os_sprs->tidr); > + if (cpu_has_feature(CPU_FTR_P9_TIDR)) > + mtspr(SPRN_TIDR, host_os_sprs->tidr); > mtspr(SPRN_IAMR, host_os_sprs->iamr); > > if (host_os_sprs->amr != vcpu->arch.amr) > diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c > index dd8241c009e5..7958e5aae844 100644 > --- a/arch/powerpc/xmon/xmon.c > +++ b/arch/powerpc/xmon/xmon.c > @@ -2107,8 +2107,14 @@ static void dump_300_sprs(void) > if (!cpu_has_feature(CPU_FTR_ARCH_300)) > return; > > - printf("pidr = %.16lx tidr = %.16lx\n", > - mfspr(SPRN_PID), mfspr(SPRN_TIDR)); > + if (cpu_has_feature(CPU_FTR_P9_TIDR)) { > + printf("pidr = %.16lx tidr = %.16lx\n", > + mfspr(SPRN_PID), mfspr(SPRN_TIDR)); > + } else { > + printf("pidr = %.16lx\n", > + mfspr(SPRN_PID)); > + } > + > printf("psscr = %.16lx\n", > hv ? mfspr(SPRN_PSSCR) : mfspr(SPRN_PSSCR_PR));
Fabiano Rosas <farosas@linux.ibm.com> writes: > Nicholas Piggin <npiggin@gmail.com> writes: > >> The TIDR SPR only exists on POWER9. Avoid accessing it when the >> feature bit for it is not set. > > Not related to this patch, but how does this work with compat mode? A P9 > compat mode guest would get an invalid instruction when trying to access > this SPR? Good question. I assume you're talking about P9 compat mode on P10. In general compat mode only applies to userspace, because it's implemented by setting the PCR which only (mostly?) applies to PR=1. I don't think there's any special casing in the ISA for the TIDR, so I think it just falls into the unimplemented SPR case for mt/fspr. That's documented in Book III section 5.4.4, in particular on page 1171 it says: Execution of this instruction specifying an SPR number that is undefined for the implementation causes one of the following. • if spr[0]=0: - if MSR[PR]=1: Hypervisor Emulation Assistance interrupt - if MSR[PR]=0: Hypervisor Emulation Assistance interrupt for SPR 0,4,5, and 6, and no operation (i.e., the instruction is treated as a no-op) when LPCR[EVIRT]=0 and Hypervisor Emulation Assistance interrupt when LPCR[EVIRT]=1 for all other SPRs Linux doesn't set EVIRT, and I assume neither does phyp, so it behaves like a nop. We actually use that behaviour in xmon to detect that an SPR is not implemented, by noticing that the mfspr has no effect on the target register, see dump_one_spr(). We should really write some docs on compat mode in the linuxppc wiki and/or Documentation ;) cheers
Michael Ellerman <mpe@ellerman.id.au> writes: > Fabiano Rosas <farosas@linux.ibm.com> writes: >> Nicholas Piggin <npiggin@gmail.com> writes: >> >>> The TIDR SPR only exists on POWER9. Avoid accessing it when the >>> feature bit for it is not set. >> >> Not related to this patch, but how does this work with compat mode? A P9 >> compat mode guest would get an invalid instruction when trying to access >> this SPR? > > Good question. > > I assume you're talking about P9 compat mode on P10. > > In general compat mode only applies to userspace, because it's > implemented by setting the PCR which only (mostly?) applies to PR=1. > > I don't think there's any special casing in the ISA for the TIDR, so I > think it just falls into the unimplemented SPR case for mt/fspr. > > That's documented in Book III section 5.4.4, in particular on page 1171 > it says: > > Execution of this instruction specifying an SPR number > that is undefined for the implementation causes one of > the following. > • if spr[0]=0: > - if MSR[PR]=1: Hypervisor Emulation Assistance interrupt > - if MSR[PR]=0: Hypervisor Emulation Assistance interrupt for SPR > 0,4,5, and 6, and no operation (i.e., the instruction is treated > as a no-op) when LPCR[EVIRT]=0 and Hypervisor Emulation Assistance > interrupt when LPCR[EVIRT]=1 for all other SPRs I knew this must have been somewhere in there but had no idea how to find it. Thanks. > Linux doesn't set EVIRT, and I assume neither does phyp, so it behaves > like a nop. > > We actually use that behaviour in xmon to detect that an SPR is not > implemented, by noticing that the mfspr has no effect on the target > register, see dump_one_spr(). > > We should really write some docs on compat mode in the linuxppc wiki > and/or Documentation ;) Hmm I was not aware we had a wiki. I'll see if I can contribute something. I need to go learn all this stuff first, though =D. > > cheers
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c index 2acb1c96cfaf..f4a779fffd18 100644 --- a/arch/powerpc/kvm/book3s_hv.c +++ b/arch/powerpc/kvm/book3s_hv.c @@ -3767,7 +3767,8 @@ static void load_spr_state(struct kvm_vcpu *vcpu) mtspr(SPRN_EBBHR, vcpu->arch.ebbhr); mtspr(SPRN_EBBRR, vcpu->arch.ebbrr); mtspr(SPRN_BESCR, vcpu->arch.bescr); - mtspr(SPRN_TIDR, vcpu->arch.tid); + if (cpu_has_feature(CPU_FTR_P9_TIDR)) + mtspr(SPRN_TIDR, vcpu->arch.tid); mtspr(SPRN_AMR, vcpu->arch.amr); mtspr(SPRN_UAMOR, vcpu->arch.uamor); @@ -3793,7 +3794,8 @@ static void store_spr_state(struct kvm_vcpu *vcpu) vcpu->arch.ebbhr = mfspr(SPRN_EBBHR); vcpu->arch.ebbrr = mfspr(SPRN_EBBRR); vcpu->arch.bescr = mfspr(SPRN_BESCR); - vcpu->arch.tid = mfspr(SPRN_TIDR); + if (cpu_has_feature(CPU_FTR_P9_TIDR)) + vcpu->arch.tid = mfspr(SPRN_TIDR); vcpu->arch.amr = mfspr(SPRN_AMR); vcpu->arch.uamor = mfspr(SPRN_UAMOR); vcpu->arch.dscr = mfspr(SPRN_DSCR); @@ -3813,7 +3815,8 @@ struct p9_host_os_sprs { static void save_p9_host_os_sprs(struct p9_host_os_sprs *host_os_sprs) { host_os_sprs->dscr = mfspr(SPRN_DSCR); - host_os_sprs->tidr = mfspr(SPRN_TIDR); + if (cpu_has_feature(CPU_FTR_P9_TIDR)) + host_os_sprs->tidr = mfspr(SPRN_TIDR); host_os_sprs->iamr = mfspr(SPRN_IAMR); host_os_sprs->amr = mfspr(SPRN_AMR); host_os_sprs->fscr = mfspr(SPRN_FSCR); @@ -3827,7 +3830,8 @@ static void restore_p9_host_os_sprs(struct kvm_vcpu *vcpu, mtspr(SPRN_UAMOR, 0); mtspr(SPRN_DSCR, host_os_sprs->dscr); - mtspr(SPRN_TIDR, host_os_sprs->tidr); + if (cpu_has_feature(CPU_FTR_P9_TIDR)) + mtspr(SPRN_TIDR, host_os_sprs->tidr); mtspr(SPRN_IAMR, host_os_sprs->iamr); if (host_os_sprs->amr != vcpu->arch.amr) diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c index dd8241c009e5..7958e5aae844 100644 --- a/arch/powerpc/xmon/xmon.c +++ b/arch/powerpc/xmon/xmon.c @@ -2107,8 +2107,14 @@ static void dump_300_sprs(void) if (!cpu_has_feature(CPU_FTR_ARCH_300)) return; - printf("pidr = %.16lx tidr = %.16lx\n", - mfspr(SPRN_PID), mfspr(SPRN_TIDR)); + if (cpu_has_feature(CPU_FTR_P9_TIDR)) { + printf("pidr = %.16lx tidr = %.16lx\n", + mfspr(SPRN_PID), mfspr(SPRN_TIDR)); + } else { + printf("pidr = %.16lx\n", + mfspr(SPRN_PID)); + } + printf("psscr = %.16lx\n", hv ? mfspr(SPRN_PSSCR) : mfspr(SPRN_PSSCR_PR));
The TIDR SPR only exists on POWER9. Avoid accessing it when the feature bit for it is not set. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> --- arch/powerpc/kvm/book3s_hv.c | 12 ++++++++---- arch/powerpc/xmon/xmon.c | 10 ++++++++-- 2 files changed, 16 insertions(+), 6 deletions(-)