From patchwork Thu Jun 7 08:06:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Mackerras X-Patchwork-Id: 926186 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ozlabs.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=ozlabs.org header.i=@ozlabs.org header.b="xHGrxIlg"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 411dTS43mgz9s31 for ; Thu, 7 Jun 2018 18:08:28 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753372AbeFGIIY (ORCPT ); Thu, 7 Jun 2018 04:08:24 -0400 Received: from ozlabs.org ([203.11.71.1]:44937 "EHLO ozlabs.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753102AbeFGIIM (ORCPT ); Thu, 7 Jun 2018 04:08:12 -0400 Received: by ozlabs.org (Postfix, from userid 1003) id 411dT70zt9z9s31; Thu, 7 Jun 2018 18:08:10 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ozlabs.org; s=201707; t=1528358891; bh=uWwPEiEnOJfQIwFStg0JOn5DUNjmh3EjrlDM5eGa7kQ=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=xHGrxIlghf2FXIAhxLlJKHqo+S7c2tsEZrI7Ez947jeSZ/h5qCKyEeoe0m8SMhgP7 z6T+8VsAgV3Oh8/oC3fxt3Q459f18b4/Vz8YM0hnnVfWVt/at5jq2u6ka4STcK1hfh rl4YI6NzvxPBzBJOF/KhOVKffpaOJBp1oz6pr2m9Hto8Iy5TvJlBoRwlgpZimnwuuJ S+qe4cPL5NBznE4LKdu7PE9Ltu265cCnSio9v5zgXRTtIQrw1KwWEY/x46XtiVczfd ccOodJVQ/ejCxe2jl9KRJb6UY+22bTzI53kleRerYDLDNYwLsLOt6owE7WNW+iRkks hpzFEEzArPMJA== Date: Thu, 7 Jun 2018 18:06:21 +1000 From: Paul Mackerras To: kvm@vger.kernel.org, kvm-ppc@vger.kernel.org Cc: Simon Guo Subject: [PATCH 2/4] KVM: PPC: Book3S PR: Fix failure status setting in treclaim. emulation Message-ID: <20180607080621.GB13401@fergus.ozlabs.ibm.com> References: <20180607080437.GA13401@fergus.ozlabs.ibm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20180607080437.GA13401@fergus.ozlabs.ibm.com> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org The treclaim. emulation needs to record failure status in the TEXASR register if the transaction had not previously failed. However, the current code first does kvmppc_save_tm_pr() (which does a treclaim. itself) and then checks the failure summary bit in TEXASR after that. Since treclaim. itself causes transaction failure, the FS bit is always set, so we were never updating TEXASR with the failure cause supplied by the guest as the RA parameter to the treclaim. instruction. This caused the tm-unavailable test in tools/testing/selftests/powerpc/tm to fail. To fix this, we need to read TEXASR before calling kvmppc_save_tm_pr(), and base the final value of TEXASR on that value. Fixes: 03c81682a90b ("KVM: PPC: Book3S PR: Add emulation for treclaim.") Signed-off-by: Paul Mackerras Reviewed-by: Simon Guo Signed-off-by: Simon Guo --- This patch is against my kvm-ppc-next branch. arch/powerpc/kvm/book3s_emulate.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/arch/powerpc/kvm/book3s_emulate.c b/arch/powerpc/kvm/book3s_emulate.c index fdbc695038dc..05cac5ea79c5 100644 --- a/arch/powerpc/kvm/book3s_emulate.c +++ b/arch/powerpc/kvm/book3s_emulate.c @@ -138,6 +138,7 @@ static void kvmppc_emulate_treclaim(struct kvm_vcpu *vcpu, int ra_val) { unsigned long guest_msr = kvmppc_get_msr(vcpu); int fc_val = ra_val ? ra_val : 1; + uint64_t texasr; /* CR0 = 0 | MSR[TS] | 0 */ vcpu->arch.cr = (vcpu->arch.cr & ~(CR0_MASK << CR0_SHIFT)) | @@ -145,25 +146,26 @@ static void kvmppc_emulate_treclaim(struct kvm_vcpu *vcpu, int ra_val) << CR0_SHIFT); preempt_disable(); + tm_enable(); + texasr = mfspr(SPRN_TEXASR); kvmppc_save_tm_pr(vcpu); kvmppc_copyfrom_vcpu_tm(vcpu); - tm_enable(); - vcpu->arch.texasr = mfspr(SPRN_TEXASR); /* failure recording depends on Failure Summary bit */ - if (!(vcpu->arch.texasr & TEXASR_FS)) { - vcpu->arch.texasr &= ~TEXASR_FC; - vcpu->arch.texasr |= ((u64)fc_val << TEXASR_FC_LG); + if (!(texasr & TEXASR_FS)) { + texasr &= ~TEXASR_FC; + texasr |= ((u64)fc_val << TEXASR_FC_LG) | TEXASR_FS; - vcpu->arch.texasr &= ~(TEXASR_PR | TEXASR_HV); + texasr &= ~(TEXASR_PR | TEXASR_HV); if (kvmppc_get_msr(vcpu) & MSR_PR) - vcpu->arch.texasr |= TEXASR_PR; + texasr |= TEXASR_PR; if (kvmppc_get_msr(vcpu) & MSR_HV) - vcpu->arch.texasr |= TEXASR_HV; + texasr |= TEXASR_HV; + vcpu->arch.texasr = texasr; vcpu->arch.tfiar = kvmppc_get_pc(vcpu); - mtspr(SPRN_TEXASR, vcpu->arch.texasr); + mtspr(SPRN_TEXASR, texasr); mtspr(SPRN_TFIAR, vcpu->arch.tfiar); } tm_disable();