From patchwork Fri Apr 8 15:54:11 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Huth X-Patchwork-Id: 608071 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3qhPCX0LQWz9t5m for ; Sat, 9 Apr 2016 01:54:16 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754046AbcDHPyP (ORCPT ); Fri, 8 Apr 2016 11:54:15 -0400 Received: from mx1.redhat.com ([209.132.183.28]:37731 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751924AbcDHPyO (ORCPT ); Fri, 8 Apr 2016 11:54:14 -0400 Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id E29A8C05E154; Fri, 8 Apr 2016 15:54:13 +0000 (UTC) Received: from thh440s.fritz.box (vpn1-7-57.ams2.redhat.com [10.36.7.57]) by int-mx14.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u38FsBok025968; Fri, 8 Apr 2016 11:54:12 -0400 From: Thomas Huth To: Michael Ellerman , Paul Mackerras , linuxppc-dev@lists.ozlabs.org Cc: Benjamin Herrenschmidt , kvm-ppc@vger.kernel.org Subject: [PATCH] powerpc: Fix definition of SIAR register Date: Fri, 8 Apr 2016 17:54:11 +0200 Message-Id: <1460130851-29021-1-git-send-email-thuth@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.27 Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org The SIAR register is available twice, one time as SPR 780 (unprivileged, but read-only), and one time as SPR 796 (privileged, but read and write). The Linux kernel code currently uses SPR 780 - and while this is OK for reading, writing to that register of course does not work. Since the KVM code tries to write to this register, too (see the mtspr in book3s_hv_rmhandlers.S), the contents of this register sometimes get lost for the guests, e.g. during migration of a VM. To fix this issue, simply switch to the other SPR numer 796 instead. Signed-off-by: Thomas Huth --- Note: The perf code in core-book3s.c also seems to write to the SIAR SPR, so that might be affected by this issue, too - but I did not test the perf code, so I'm not sure about that part. arch/powerpc/include/asm/reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index f5f4c66..6630420 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -752,13 +752,13 @@ #define SPRN_PMC6 792 #define SPRN_PMC7 793 #define SPRN_PMC8 794 -#define SPRN_SIAR 780 #define SPRN_SDAR 781 #define SPRN_SIER 784 #define SIER_SIPR 0x2000000 /* Sampled MSR_PR */ #define SIER_SIHV 0x1000000 /* Sampled MSR_HV */ #define SIER_SIAR_VALID 0x0400000 /* SIAR contents valid */ #define SIER_SDAR_VALID 0x0200000 /* SDAR contents valid */ +#define SPRN_SIAR 796 #define SPRN_TACR 888 #define SPRN_TCSCR 889 #define SPRN_CSIGR 890