From patchwork Tue Jul 8 06:38:20 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 367803 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3713C1400B8 for ; Tue, 8 Jul 2014 16:38:41 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752836AbaGHGik (ORCPT ); Tue, 8 Jul 2014 02:38:40 -0400 Received: from mail-pd0-f180.google.com ([209.85.192.180]:63549 "EHLO mail-pd0-f180.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751566AbaGHGij (ORCPT ); Tue, 8 Jul 2014 02:38:39 -0400 Received: by mail-pd0-f180.google.com with SMTP id fp1so6673219pdb.11 for ; Mon, 07 Jul 2014 23:38:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=jms.id.au; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hXizau0tM+2SlqmOjpZiBLLj4e5/iatvjzJLYxJnT5M=; b=JmPNRNUoXzzfmHJ928wqhuNUGrPqTUUrCc1qSEBIQQ8uog1Nuhqjdg+ZUy7ue74YnI x/+9clX1+32il7n2sf63uPaLjmxGEdcIYJpL95Hy6RyaQXFEqjGeaO4E/hUUMOWPiJhy 6fNGxTP2qwG5YaOFe/GmB6g4ij9/nuElIUi1I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hXizau0tM+2SlqmOjpZiBLLj4e5/iatvjzJLYxJnT5M=; b=d7MKNwdAV+ZRM9tz5tsroifLasmRm3FLvsT9nmJk+fpQ+twDep+QJAWCLAqsutPJa6 sAKzPOzIC95YYiPAKCV0BKCiHPIsbXxwlIqpqhGwmy5oJ+XXB1OrTZqcBowRNAgzOKyR 0TKQidHuDAwQmFA8cpfE+nI09VXSbtLL1z4EbYo3EcmghjYUDgIrFcLsirPcGKmtRqkP r3+OpdpxexcjAvmV42mZwsepVxbK9HHCoPp1NWJ+adS/npls9b/7tk/UUDEp47rH/Ydj vfeG9fnLbmpSKPBzBmsgqXd76CB5PjwW+WW2e9abzOpwSd/mcGAFFOcCnns4O/ECzk79 Kl/A== X-Gm-Message-State: ALoCoQnTAjNrkIZWz4rZuK6wCYkafzj7FiOli9TsWLt38cC329O7GKcmoxESCSDG9sorFJcq3Yho X-Received: by 10.66.234.202 with SMTP id ug10mr7755319pac.109.1404801518575; Mon, 07 Jul 2014 23:38:38 -0700 (PDT) Received: from icarus.au.ibm.com (ppp14-2-14-154.lns21.adl2.internode.on.net. [14.2.14.154]) by mx.google.com with ESMTPSA id rb8sm74064931pab.27.2014.07.07.23.38.35 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Jul 2014 23:38:38 -0700 (PDT) From: Joel Stanley To: benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au, Alexander Graf Cc: linuxppc-dev@lists.ozlabs.org, kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH v2 1/3] powerpc/kvm: Remove redundant save of SIER AND MMCR2 Date: Tue, 8 Jul 2014 16:08:20 +0930 Message-Id: <1404801502-4663-2-git-send-email-joel@jms.id.au> X-Mailer: git-send-email 2.0.0 In-Reply-To: <1404801502-4663-1-git-send-email-joel@jms.id.au> References: <1404801502-4663-1-git-send-email-joel@jms.id.au> Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org These two registers are already saved in the block above. Aside from being unnecessary, by the time we get down to the second save location r8 no longer contains MMCR2, so we are clobbering the saved value with PMC5. MMCR2 primarily consists of counter freeze bits. So restoring the value of PMC5 into MMCR2 will most likely have the effect of freezing counters. Fixes: 72cde5a88d37 ("KVM: PPC: Book3S HV: Save/restore host PMU registers that are new in POWER8") Cc: stable@vger.kernel.org Signed-off-by: Joel Stanley Acked-by: Michael Ellerman Acked-by: Paul Mackerras Reviewed-by: Alexander Graf --- V2: - Add comments from mpe arch/powerpc/kvm/book3s_hv_interrupts.S | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/powerpc/kvm/book3s_hv_interrupts.S b/arch/powerpc/kvm/book3s_hv_interrupts.S index 8c86422..731be74 100644 --- a/arch/powerpc/kvm/book3s_hv_interrupts.S +++ b/arch/powerpc/kvm/book3s_hv_interrupts.S @@ -127,11 +127,6 @@ BEGIN_FTR_SECTION stw r10, HSTATE_PMC + 24(r13) stw r11, HSTATE_PMC + 28(r13) END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201) -BEGIN_FTR_SECTION - mfspr r9, SPRN_SIER - std r8, HSTATE_MMCR + 40(r13) - std r9, HSTATE_MMCR + 48(r13) -END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S) 31: /*