From patchwork Mon Jun 30 12:54:58 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mihai Caraman X-Patchwork-Id: 365584 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 0AF86140082 for ; Mon, 30 Jun 2014 22:55:10 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752104AbaF3MzJ (ORCPT ); Mon, 30 Jun 2014 08:55:09 -0400 Received: from mail-bn1blp0185.outbound.protection.outlook.com ([207.46.163.185]:35580 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752033AbaF3MzH (ORCPT ); Mon, 30 Jun 2014 08:55:07 -0400 Received: from DM2PR03CA004.namprd03.prod.outlook.com (10.141.52.152) by BLUPR03MB501.namprd03.prod.outlook.com (10.141.80.18) with Microsoft SMTP Server (TLS) id 15.0.959.24; Mon, 30 Jun 2014 12:55:05 +0000 Received: from BN1AFFO11FD060.protection.gbl (2a01:111:f400:7c10::128) by DM2PR03CA004.outlook.office365.com (2a01:111:e400:2414::24) with Microsoft SMTP Server (TLS) id 15.0.974.11 via Frontend Transport; Mon, 30 Jun 2014 12:55:04 +0000 Received: from az84smr01.freescale.net (192.88.158.2) by BN1AFFO11FD060.mail.protection.outlook.com (10.58.53.75) with Microsoft SMTP Server (TLS) id 15.0.969.12 via Frontend Transport; Mon, 30 Jun 2014 12:55:04 +0000 Received: from fsr-fed1764-012.ea.freescale.net (fsr-fed1764-012-010171073213.ea.freescale.net [10.171.73.213]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s5UCt1Y0018406; Mon, 30 Jun 2014 05:55:02 -0700 From: Mihai Caraman To: CC: , , Mihai Caraman Subject: [PATCH] KVM: PPC: e500: Fix default tlb for victim hint Date: Mon, 30 Jun 2014 15:54:58 +0300 Message-ID: <1404132898-27261-1-git-send-email-mihai.caraman@freescale.com> X-Mailer: git-send-email 1.7.11.7 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.2; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(6009001)(189002)(199002)(74502001)(50226001)(88136002)(19580405001)(68736004)(89996001)(81342001)(77982001)(104166001)(4396001)(44976005)(36756003)(87936001)(31966008)(229853001)(6806004)(95666004)(74662001)(19580395003)(50986999)(21056001)(87286001)(69596002)(104016002)(46102001)(76482001)(64706001)(20776003)(85852003)(83072002)(575784001)(77156001)(62966002)(50466002)(80022001)(47776003)(92726001)(86362001)(93916002)(92566001)(106466001)(105606002)(81156004)(48376002)(85306003)(102836001)(79102001)(99396002)(26826002)(84676001)(97736001)(107046002)(81542001)(83322001)(33646001)(2351001); DIR:OUT; SFP:; SCL:1; SRVR:BLUPR03MB501; H:az84smr01.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID: X-Forefront-PRVS: 0258E7CCD4 Received-SPF: Fail (: domain of freescale.com does not designate 192.88.158.2 as permitted sender) receiver=; client-ip=192.88.158.2; helo=az84smr01.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.158.2) smtp.mailfrom=mihai.caraman@freescale.com; X-OriginatorOrg: freescale.com Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org Tlb search operation used for victim hint relies on the default tlb set by the host. When hardware tablewalk support is enabled in the host, the default tlb is TLB1 which leads KVM to evict the bolted entry. Set and restore the default tlb when searching for victim hint. Signed-off-by: Mihai Caraman Reviewed-by: Scott Wood --- arch/powerpc/include/asm/mmu-book3e.h | 5 ++++- arch/powerpc/kvm/e500_mmu_host.c | 4 ++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h index 901dac6..5dad378 100644 --- a/arch/powerpc/include/asm/mmu-book3e.h +++ b/arch/powerpc/include/asm/mmu-book3e.h @@ -40,7 +40,9 @@ /* MAS registers bit definitions */ -#define MAS0_TLBSEL(x) (((x) << 28) & 0x30000000) +#define MAS0_TLBSEL_MASK 0x30000000 +#define MAS0_TLBSEL_SHIFT 28 +#define MAS0_TLBSEL(x) (((x) << MAS0_TLBSEL_SHIFT) & MAS0_TLBSEL_MASK) #define MAS0_ESEL_MASK 0x0FFF0000 #define MAS0_ESEL_SHIFT 16 #define MAS0_ESEL(x) (((x) << MAS0_ESEL_SHIFT) & MAS0_ESEL_MASK) @@ -86,6 +88,7 @@ #define MAS3_SPSIZE 0x0000003e #define MAS3_SPSIZE_SHIFT 1 +#define MAS4_TLBSEL_MASK MAS0_TLBSEL_MASK #define MAS4_TLBSELD(x) MAS0_TLBSEL(x) #define MAS4_INDD 0x00008000 /* Default IND */ #define MAS4_TSIZED(x) MAS1_TSIZE(x) diff --git a/arch/powerpc/kvm/e500_mmu_host.c b/arch/powerpc/kvm/e500_mmu_host.c index dd2cc03..79677d7 100644 --- a/arch/powerpc/kvm/e500_mmu_host.c +++ b/arch/powerpc/kvm/e500_mmu_host.c @@ -107,11 +107,15 @@ static u32 get_host_mas0(unsigned long eaddr) { unsigned long flags; u32 mas0; + u32 mas4; local_irq_save(flags); mtspr(SPRN_MAS6, 0); + mas4 = mfspr(SPRN_MAS4); + mtspr(SPRN_MAS4, mas4 & ~MAS4_TLBSEL_MASK); asm volatile("tlbsx 0, %0" : : "b" (eaddr & ~CONFIG_PAGE_OFFSET)); mas0 = mfspr(SPRN_MAS0); + mtspr(SPRN_MAS4, mas4); local_irq_restore(flags); return mas0;