From patchwork Thu May 1 00:45:50 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mihai Caraman X-Patchwork-Id: 344376 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 0744A140117 for ; Thu, 1 May 2014 10:46:06 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753318AbaEAAqE (ORCPT ); Wed, 30 Apr 2014 20:46:04 -0400 Received: from mail-bn1blp0183.outbound.protection.outlook.com ([207.46.163.183]:53442 "EHLO na01-bn1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753315AbaEAAqC (ORCPT ); Wed, 30 Apr 2014 20:46:02 -0400 Received: from BL2PR03CA022.namprd03.prod.outlook.com (10.141.66.30) by BL2PR03MB499.namprd03.prod.outlook.com (10.141.93.147) with Microsoft SMTP Server (TLS) id 15.0.934.12; Thu, 1 May 2014 00:46:00 +0000 Received: from BY2FFO11FD033.protection.gbl (2a01:111:f400:7c0c::139) by BL2PR03CA022.outlook.office365.com (2a01:111:e400:c1b::30) with Microsoft SMTP Server (TLS) id 15.0.929.12 via Frontend Transport; Thu, 1 May 2014 00:45:59 +0000 Received: from az84smr01.freescale.net (192.88.158.246) by BY2FFO11FD033.mail.protection.outlook.com (10.1.14.218) with Microsoft SMTP Server (TLS) id 15.0.929.8 via Frontend Transport; Thu, 1 May 2014 00:45:59 +0000 Received: from fsr-fed1764-012.ea.freescale.net (fsr-fed1764-012-010171073213.ea.freescale.net [10.171.73.213]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s410jsZO008245; Wed, 30 Apr 2014 17:45:57 -0700 From: Mihai Caraman To: CC: , , Mihai Caraman Subject: [PATCH v2 2/4] KVM: PPC: Book3e: Add TLBSEL/TSIZE defines for MAS0/1 Date: Thu, 1 May 2014 03:45:50 +0300 Message-ID: <1398905152-18091-3-git-send-email-mihai.caraman@freescale.com> X-Mailer: git-send-email 1.7.11.7 In-Reply-To: <1398905152-18091-1-git-send-email-mihai.caraman@freescale.com> References: <1398905152-18091-1-git-send-email-mihai.caraman@freescale.com> X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.158.246; CTRY:US; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10009001)(6009001)(428001)(189002)(199002)(47776003)(20776003)(6806004)(80022001)(81542001)(33646001)(79102001)(74502001)(50466002)(575784001)(48376002)(50226001)(93916002)(92566001)(99396002)(86362001)(4396001)(92726001)(76482001)(89996001)(77982001)(77096999)(31966008)(46102001)(83072002)(74662001)(101416001)(80976001)(87936001)(81342001)(44976005)(87286001)(62966002)(76176999)(77156001)(88136002)(83322001)(19580405001)(19580395003)(36756003)(50986999)(32563001); DIR:OUT; SFP:1101; SCL:1; SRVR:BL2PR03MB499; H:az84smr01.freescale.net; FPR:; MLV:sfv; PTR:gate-az5.freescale.com; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Forefront-PRVS: 01986AE76B Received-SPF: None (: freescale.com does not designate permitted sender hosts) Authentication-Results: spf=none (sender IP is 192.88.158.246) smtp.mailfrom=mihai.caraman@freescale.com; X-OriginatorOrg: freescale.com Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org Add defines MAS0_GET_TLBSEL() and MAS1_GET_TSIZE() to Book3E. Signed-off-by: Mihai Caraman --- v2: - no change arch/powerpc/include/asm/mmu-book3e.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h index 901dac6..60a949a 100644 --- a/arch/powerpc/include/asm/mmu-book3e.h +++ b/arch/powerpc/include/asm/mmu-book3e.h @@ -40,7 +40,11 @@ /* MAS registers bit definitions */ -#define MAS0_TLBSEL(x) (((x) << 28) & 0x30000000) +#define MAS0_TLBSEL_MASK 0x30000000 +#define MAS0_TLBSEL_SHIFT 28 +#define MAS0_TLBSEL(x) (((x) << MAS0_TLBSEL_SHIFT) & MAS0_TLBSEL_MASK) +#define MAS0_GET_TLBSEL(mas0) (((mas0) & MAS0_TLBSEL_MASK) >> \ + MAS0_TLBSEL_SHIFT) #define MAS0_ESEL_MASK 0x0FFF0000 #define MAS0_ESEL_SHIFT 16 #define MAS0_ESEL(x) (((x) << MAS0_ESEL_SHIFT) & MAS0_ESEL_MASK) @@ -58,6 +62,7 @@ #define MAS1_TSIZE_MASK 0x00000f80 #define MAS1_TSIZE_SHIFT 7 #define MAS1_TSIZE(x) (((x) << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK) +#define MAS1_GET_TSIZE(mas1) (((mas1) & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT) #define MAS2_EPN (~0xFFFUL) #define MAS2_X0 0x00000040