From patchwork Thu Feb 20 16:30:19 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mihai Caraman X-Patchwork-Id: 322254 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 902692C00E8 for ; Fri, 21 Feb 2014 03:30:48 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754988AbaBTQan (ORCPT ); Thu, 20 Feb 2014 11:30:43 -0500 Received: from va3ehsobe002.messaging.microsoft.com ([216.32.180.12]:25993 "EHLO va3outboundpool.messaging.microsoft.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754889AbaBTQak (ORCPT ); Thu, 20 Feb 2014 11:30:40 -0500 Received: from mail20-va3-R.bigfish.com (10.7.14.226) by VA3EHSOBE001.bigfish.com (10.7.40.21) with Microsoft SMTP Server id 14.1.225.22; Thu, 20 Feb 2014 16:30:39 +0000 Received: from mail20-va3 (localhost [127.0.0.1]) by mail20-va3-R.bigfish.com (Postfix) with ESMTP id 33EBA2201B3; Thu, 20 Feb 2014 16:30:39 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 3 X-BigFish: VS3(zcb8kze0eahzz1f42h2148h208ch1ee6h1de0h1fdah2073h2146h1202h1e76h2189h1d1ah1d2ah21bch1fc6hzz1de098h8275bh1de097hz2dh2a8h839hd24he5bhf0ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1504h1537h162dh1631h1758h1898h18e1h1946h19b5h1ad9h1b0ah1b2fh2222h224fh1fb3h1d0ch1d2eh1d3fh1dfeh1dffh1e23h1fe8h1ff5h2218h2216h226dh22d0h24afh2327h2336h2438h2461h2487h24d7h2516h2545h255eh1155h) Received: from mail20-va3 (localhost.localdomain [127.0.0.1]) by mail20-va3 (MessageSwitch) id 1392913836609021_8568; Thu, 20 Feb 2014 16:30:36 +0000 (UTC) Received: from VA3EHSMHS016.bigfish.com (unknown [10.7.14.234]) by mail20-va3.bigfish.com (Postfix) with ESMTP id 8773EA00DB; Thu, 20 Feb 2014 16:30:36 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by VA3EHSMHS016.bigfish.com (10.7.99.26) with Microsoft SMTP Server (TLS) id 14.16.227.3; Thu, 20 Feb 2014 16:30:35 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-004.039d.mgd.msft.net (10.84.1.14) with Microsoft SMTP Server (TLS) id 14.3.158.2; Thu, 20 Feb 2014 16:30:32 +0000 Received: from fsr-fed1364-13.ea.freescale.net (fsr-fed1364-13.ea.freescale.net [10.171.81.124]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id s1KGUOIP009773; Thu, 20 Feb 2014 09:30:31 -0700 From: Mihai Caraman To: CC: , , Mihai Caraman Subject: [PATCH 2/4] KVM: PPC: Book3e: Add TLBSEL/TSIZE defines for MAS0/1 Date: Thu, 20 Feb 2014 18:30:19 +0200 Message-ID: <1392913821-4520-2-git-send-email-mihai.caraman@freescale.com> X-Mailer: git-send-email 1.7.3.4 In-Reply-To: <1392913821-4520-1-git-send-email-mihai.caraman@freescale.com> References: <1392913821-4520-1-git-send-email-mihai.caraman@freescale.com> MIME-Version: 1.0 X-OriginatorOrg: freescale.com X-FOPE-CONNECTOR: Id%0$Dn%*$RO%0$TLS%0$FQDN%$TlsDn% X-FOPE-CONNECTOR: Id%0$Dn%FREESCALE.MAIL.ONMICROSOFT.COM$RO%1$TLS%0$FQDN%$TlsDn% Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org Add mising defines MAS0_GET_TLBSEL() and MAS1_GET_TSIZE() for Book3E. Signed-off-by: Mihai Caraman --- arch/powerpc/include/asm/mmu-book3e.h | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/include/asm/mmu-book3e.h b/arch/powerpc/include/asm/mmu-book3e.h index 936db36..2b23313 100644 --- a/arch/powerpc/include/asm/mmu-book3e.h +++ b/arch/powerpc/include/asm/mmu-book3e.h @@ -40,7 +40,10 @@ /* MAS registers bit definitions */ -#define MAS0_TLBSEL(x) (((x) << 28) & 0x30000000) +#define MAS0_TLBSEL_MASK 0x30000000 +#define MAS0_TLBSEL_SHIFT 28 +#define MAS0_TLBSEL(x) (((x) << MAS0_TLBSEL_SHIFT) & MAS0_TLBSEL_MASK) +#define MAS0_GET_TLBSEL(mas0) (((mas0) & MAS0_TLBSEL_MASK) >> MAS0_TLBSEL_SHIFT) #define MAS0_ESEL_MASK 0x0FFF0000 #define MAS0_ESEL_SHIFT 16 #define MAS0_ESEL(x) (((x) << MAS0_ESEL_SHIFT) & MAS0_ESEL_MASK) @@ -58,6 +61,7 @@ #define MAS1_TSIZE_MASK 0x00000f80 #define MAS1_TSIZE_SHIFT 7 #define MAS1_TSIZE(x) (((x) << MAS1_TSIZE_SHIFT) & MAS1_TSIZE_MASK) +#define MAS1_GET_TSIZE(mas1) (((mas1) & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT) #define MAS2_EPN (~0xFFFUL) #define MAS2_X0 0x00000040