| Message ID | 20240818083250.3153977-1-sasha.neftin@intel.com |
|---|---|
| State | Accepted |
| Delegated to: | Anthony Nguyen |
| Headers | show |
| Series | [iwl-next,v1,1/1] igc: Move the MULTI GBT AN Control Register to _regs file | expand |
Dear Sasha, Thank you for the patch. Am 18.08.24 um 10:32 schrieb Sasha Neftin: > MULTI GBT AN Control Register is IEEE Standard Register 7.32 (not a mask). > The right place should be in igc_reg.h file. In accordance with the > registers naming convention added IGC_' prefix. > > Signed-off-by: Sasha Neftin <sasha.neftin@intel.com> > --- > drivers/net/ethernet/intel/igc/igc_defines.h | 1 - > drivers/net/ethernet/intel/igc/igc_phy.c | 4 ++-- > drivers/net/ethernet/intel/igc/igc_regs.h | 3 +++ > 3 files changed, 5 insertions(+), 3 deletions(-) > > diff --git a/drivers/net/ethernet/intel/igc/igc_defines.h b/drivers/net/ethernet/intel/igc/igc_defines.h > index 6d6717ba4ffd..8e449904aa7d 100644 > --- a/drivers/net/ethernet/intel/igc/igc_defines.h > +++ b/drivers/net/ethernet/intel/igc/igc_defines.h > @@ -178,7 +178,6 @@ > > /* PHY GPY 211 registers */ > #define STANDARD_AN_REG_MASK 0x0007 /* MMD */ > -#define ANEG_MULTIGBT_AN_CTRL 0x0020 /* MULTI GBT AN Control Register */ > #define MMD_DEVADDR_SHIFT 16 /* Shift MMD to higher bits */ > #define CR_2500T_FD_CAPS 0x0080 /* Advertise 2500T FD capability */ > > diff --git a/drivers/net/ethernet/intel/igc/igc_phy.c b/drivers/net/ethernet/intel/igc/igc_phy.c > index 861f37076861..2801e5f24df9 100644 > --- a/drivers/net/ethernet/intel/igc/igc_phy.c > +++ b/drivers/net/ethernet/intel/igc/igc_phy.c > @@ -240,7 +240,7 @@ static s32 igc_phy_setup_autoneg(struct igc_hw *hw) > /* Read the MULTI GBT AN Control Register - reg 7.32 */ > ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK << > MMD_DEVADDR_SHIFT) | > - ANEG_MULTIGBT_AN_CTRL, > + IGC_ANEG_MULTIGBT_AN_CTRL, > &aneg_multigbt_an_ctrl); > > if (ret_val) > @@ -380,7 +380,7 @@ static s32 igc_phy_setup_autoneg(struct igc_hw *hw) > ret_val = phy->ops.write_reg(hw, > (STANDARD_AN_REG_MASK << > MMD_DEVADDR_SHIFT) | > - ANEG_MULTIGBT_AN_CTRL, > + IGC_ANEG_MULTIGBT_AN_CTRL, > aneg_multigbt_an_ctrl); > > return ret_val; > diff --git a/drivers/net/ethernet/intel/igc/igc_regs.h b/drivers/net/ethernet/intel/igc/igc_regs.h > index bb6f37f5d3a5..12ddc5793651 100644 > --- a/drivers/net/ethernet/intel/igc/igc_regs.h > +++ b/drivers/net/ethernet/intel/igc/igc_regs.h > @@ -310,6 +310,9 @@ > #define IGC_IPCNFG 0x0E38 /* Internal PHY Configuration */ > #define IGC_EEE_SU 0x0E34 /* EEE Setup */ > > +/* MULTI GBT AN Control Register - reg. 7.32 */ > +#define IGC_ANEG_MULTIGBT_AN_CTRL 0x0020 > + > /* EEE ANeg Advertisement Register - reg 7.60 and reg 7.62 */ > #define IGC_ANEG_EEE_AB1 0x003c > #define IGC_ANEG_EEE_AB2 0x003e Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Kind regards, Paul
On 8/18/2024 11:32 AM, Sasha Neftin wrote: > MULTI GBT AN Control Register is IEEE Standard Register 7.32 (not a mask). > The right place should be in igc_reg.h file. In accordance with the > registers naming convention added IGC_' prefix. > > Signed-off-by: Sasha Neftin <sasha.neftin@intel.com> > Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> > --- > drivers/net/ethernet/intel/igc/igc_defines.h | 1 - > drivers/net/ethernet/intel/igc/igc_phy.c | 4 ++-- > drivers/net/ethernet/intel/igc/igc_regs.h | 3 +++ > 3 files changed, 5 insertions(+), 3 deletions(-) > Tested-by: Avigail Dahan <avigailx.dahan@intel.com>
diff --git a/drivers/net/ethernet/intel/igc/igc_defines.h b/drivers/net/ethernet/intel/igc/igc_defines.h index 6d6717ba4ffd..8e449904aa7d 100644 --- a/drivers/net/ethernet/intel/igc/igc_defines.h +++ b/drivers/net/ethernet/intel/igc/igc_defines.h @@ -178,7 +178,6 @@ /* PHY GPY 211 registers */ #define STANDARD_AN_REG_MASK 0x0007 /* MMD */ -#define ANEG_MULTIGBT_AN_CTRL 0x0020 /* MULTI GBT AN Control Register */ #define MMD_DEVADDR_SHIFT 16 /* Shift MMD to higher bits */ #define CR_2500T_FD_CAPS 0x0080 /* Advertise 2500T FD capability */ diff --git a/drivers/net/ethernet/intel/igc/igc_phy.c b/drivers/net/ethernet/intel/igc/igc_phy.c index 861f37076861..2801e5f24df9 100644 --- a/drivers/net/ethernet/intel/igc/igc_phy.c +++ b/drivers/net/ethernet/intel/igc/igc_phy.c @@ -240,7 +240,7 @@ static s32 igc_phy_setup_autoneg(struct igc_hw *hw) /* Read the MULTI GBT AN Control Register - reg 7.32 */ ret_val = phy->ops.read_reg(hw, (STANDARD_AN_REG_MASK << MMD_DEVADDR_SHIFT) | - ANEG_MULTIGBT_AN_CTRL, + IGC_ANEG_MULTIGBT_AN_CTRL, &aneg_multigbt_an_ctrl); if (ret_val) @@ -380,7 +380,7 @@ static s32 igc_phy_setup_autoneg(struct igc_hw *hw) ret_val = phy->ops.write_reg(hw, (STANDARD_AN_REG_MASK << MMD_DEVADDR_SHIFT) | - ANEG_MULTIGBT_AN_CTRL, + IGC_ANEG_MULTIGBT_AN_CTRL, aneg_multigbt_an_ctrl); return ret_val; diff --git a/drivers/net/ethernet/intel/igc/igc_regs.h b/drivers/net/ethernet/intel/igc/igc_regs.h index bb6f37f5d3a5..12ddc5793651 100644 --- a/drivers/net/ethernet/intel/igc/igc_regs.h +++ b/drivers/net/ethernet/intel/igc/igc_regs.h @@ -310,6 +310,9 @@ #define IGC_IPCNFG 0x0E38 /* Internal PHY Configuration */ #define IGC_EEE_SU 0x0E34 /* EEE Setup */ +/* MULTI GBT AN Control Register - reg. 7.32 */ +#define IGC_ANEG_MULTIGBT_AN_CTRL 0x0020 + /* EEE ANeg Advertisement Register - reg 7.60 and reg 7.62 */ #define IGC_ANEG_EEE_AB1 0x003c #define IGC_ANEG_EEE_AB2 0x003e
MULTI GBT AN Control Register is IEEE Standard Register 7.32 (not a mask). The right place should be in igc_reg.h file. In accordance with the registers naming convention added IGC_' prefix. Signed-off-by: Sasha Neftin <sasha.neftin@intel.com> --- drivers/net/ethernet/intel/igc/igc_defines.h | 1 - drivers/net/ethernet/intel/igc/igc_phy.c | 4 ++-- drivers/net/ethernet/intel/igc/igc_regs.h | 3 +++ 3 files changed, 5 insertions(+), 3 deletions(-)