| Message ID | 20240814045553.947331-1-daiweili@google.com |
|---|---|
| State | Accepted |
| Delegated to: | Anthony Nguyen |
| Headers | show |
| Series | [iwl-net,v3] igb: Fix not clearing TimeSync interrupts for 82580 | expand |
Daiwei Li <daiweili@google.com> writes: > 82580 NICs have a hardware bug that makes it > necessary to write into the TSICR (TimeSync Interrupt Cause) register > to clear it: > https://lore.kernel.org/all/CDCB8BE0.1EC2C%25matthew.vick@intel.com/ > > Add a conditional so only for 82580 we write into the TSICR register, > so we don't risk losing events for other models. > > Without this change, when running ptp4l with an Intel 82580 card, > I get the following output: > >> timed out while polling for tx timestamp increasing tx_timestamp_timeout or >> increasing kworker priority may correct this issue, but a driver bug likely >> causes it > > This goes away with this change. > > This (partially) reverts commit ee14cc9ea19b ("igb: Fix missing time sync events"). > > Fixes: ee14cc9ea19b ("igb: Fix missing time sync events") > Closes: https://lore.kernel.org/intel-wired-lan/CAN0jFd1kO0MMtOh8N2Ztxn6f7vvDKp2h507sMryobkBKe=xk=w@mail.gmail.com/ > Tested-by: Daiwei Li <daiweili@google.com> > Suggested-by: Vinicius Costa Gomes <vinicius.gomes@intel.com> > Signed-off-by: Daiwei Li <daiweili@google.com> Acked-by: Vinicius Costa Gomes <vinicius.gomes@intel.com> Cheers,
On Tue Aug 13 2024, Daiwei Li wrote: > 82580 NICs have a hardware bug that makes it > necessary to write into the TSICR (TimeSync Interrupt Cause) register > to clear it: > https://lore.kernel.org/all/CDCB8BE0.1EC2C%25matthew.vick@intel.com/ > > Add a conditional so only for 82580 we write into the TSICR register, > so we don't risk losing events for other models. > > Without this change, when running ptp4l with an Intel 82580 card, > I get the following output: > >> timed out while polling for tx timestamp increasing tx_timestamp_timeout or >> increasing kworker priority may correct this issue, but a driver bug likely >> causes it > > This goes away with this change. > > This (partially) reverts commit ee14cc9ea19b ("igb: Fix missing time sync events"). > > Fixes: ee14cc9ea19b ("igb: Fix missing time sync events") > Closes: https://lore.kernel.org/intel-wired-lan/CAN0jFd1kO0MMtOh8N2Ztxn6f7vvDKp2h507sMryobkBKe=xk=w@mail.gmail.com/ > Tested-by: Daiwei Li <daiweili@google.com> > Suggested-by: Vinicius Costa Gomes <vinicius.gomes@intel.com> > Signed-off-by: Daiwei Li <daiweili@google.com> Reviewed-by: Kurt Kanzenbach <kurt@linutronix.de>
> -----Original Message----- > From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of Daiwei Li > Sent: Wednesday, August 14, 2024 10:26 AM > To: intel-wired-lan@lists.osuosl.org > Cc: Daiwei Li <daiweili@google.com>; Neftin, Sasha <sasha.neftin@intel.com>; Gomes, Vinicius <vinicius.gomes@intel.com>; netdev@vger.kernel.org; richardcochran@gmail.com; kurt@linutronix.de; linux-kernel@vger.kernel.org; edumazet@google.com; Nguyen, Anthony L <anthony.l.nguyen@intel.com>; Kitszel, Przemyslaw <przemyslaw.kitszel@intel.com>; kuba@kernel.org; pabeni@redhat.com; davem@davemloft.net > Subject: [Intel-wired-lan] [PATCH iwl-net v3] igb: Fix not clearing TimeSync interrupts for 82580 > > 82580 NICs have a hardware bug that makes it necessary to write into the TSICR (TimeSync Interrupt Cause) register to clear it: > https://lore.kernel.org/all/CDCB8BE0.1EC2C%25matthew.vick@intel.com/ > > Add a conditional so only for 82580 we write into the TSICR register, so we don't risk losing events for other models. > > Without this change, when running ptp4l with an Intel 82580 card, I get the following output: > > > timed out while polling for tx timestamp increasing > > tx_timestamp_timeout or increasing kworker priority may correct this > > issue, but a driver bug likely causes it > > This goes away with this change. > > This (partially) reverts commit ee14cc9ea19b ("igb: Fix missing time sync events"). > > Fixes: ee14cc9ea19b ("igb: Fix missing time sync events") > Closes: https://lore.kernel.org/intel-wired-lan/CAN0jFd1kO0MMtOh8N2Ztxn6f7vvDKp2h507sMryobkBKe=xk=w@mail.gmail.com/ > Tested-by: Daiwei Li <daiweili@google.com> > Suggested-by: Vinicius Costa Gomes <vinicius.gomes@intel.com> > Signed-off-by: Daiwei Li <daiweili@google.com> > --- > drivers/net/ethernet/intel/igb/igb_main.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com> (A Contingent worker at Intel)
diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c index ada42ba63549..69d7e8b16437 100644 --- a/drivers/net/ethernet/intel/igb/igb_main.c +++ b/drivers/net/ethernet/intel/igb/igb_main.c @@ -6984,9 +6984,19 @@ static void igb_extts(struct igb_adapter *adapter, int tsintr_tt) static void igb_tsync_interrupt(struct igb_adapter *adapter) { struct e1000_hw *hw = &adapter->hw; + const u32 mask = (TSINTR_SYS_WRAP | E1000_TSICR_TXTS | + TSINTR_TT0 | TSINTR_TT1 | + TSINTR_AUTT0 | TSINTR_AUTT1); u32 tsicr = rd32(E1000_TSICR); struct ptp_clock_event event; + if (hw->mac.type == e1000_82580) { + /* 82580 has a hardware bug that requires an explicit + * write to clear the TimeSync interrupt cause. + */ + wr32(E1000_TSICR, tsicr & mask); + } + if (tsicr & TSINTR_SYS_WRAP) { event.type = PTP_CLOCK_PPS; if (adapter->ptp_caps.pps)