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Thu, 8 Aug 2024 12:58:37 +0000 (UTC) X-CSE-ConnectionGUID: 6lxPqYhQTfO2sfE1OzEyyw== X-CSE-MsgGUID: 8d2YvWUtTjaPpchvuDLcBQ== X-IronPort-AV: E=McAfee;i="6700,10204,11158"; a="21404760" X-IronPort-AV: E=Sophos;i="6.09,273,1716274800"; d="scan'208";a="21404760" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2024 05:58:34 -0700 X-CSE-ConnectionGUID: JkNpYmUaQxeGjHH0aj+fMQ== X-CSE-MsgGUID: IgB/onBcT1WrGWZn/Gttkw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.09,273,1716274800"; d="scan'208";a="61595071" Received: from unknown (HELO kkolacin-desk1.igk.intel.com) ([10.217.160.108]) by fmviesa005.fm.intel.com with ESMTP; 08 Aug 2024 05:58:33 -0700 From: Karol Kolacinski To: intel-wired-lan@lists.osuosl.org Date: Thu, 8 Aug 2024 14:57:44 +0200 Message-ID: <20240808125825.560093-10-karol.kolacinski@intel.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20240808125825.560093-8-karol.kolacinski@intel.com> References: <20240808125825.560093-8-karol.kolacinski@intel.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1723121917; x=1754657917; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+d8DdgduNTeedRsYArvK/lfw1KmycAiuex+juw2noZI=; b=edphm43TuZrGs+bJwk3Qf0Lgj8V8bLzOgHkRmkfx++T3l7BQnqgwBHE7 zAnQHr+HBmgysDTzhX4pKROq3R7W2kPy2YsWq3JozFBXIelwsqF30Xg1X /cAcZ4Q16QyAyT1+XqnuOE720LIQ/v0Bbw3JWy0g9qsDB5HhNcCVj+B+s /ofG0wpdrNiGBoaHTwgIyVCcu/3uxAvdD+KvLZefQjZJ0Wtg9P8A+cXlF WJ+XwyMuds+qMJfDluASriYxJMYmyD6FzORhvkQgxIY0x6A/OSyHe4AxL /+gE40PaSSqb+mGp7Nc3cTPMyB87m4styFVEPOsc7IHAx8+MX+GTVhIBO A==; X-Mailman-Original-Authentication-Results: smtp3.osuosl.org; dmarc=pass (p=none dis=none) header.from=intel.com X-Mailman-Original-Authentication-Results: smtp3.osuosl.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=edphm43T Subject: [Intel-wired-lan] [PATCH v5 iwl-next 2/6] ice: Use FIELD_PREP for timestamp values X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: netdev@vger.kernel.org, Karol Kolacinski , anthony.l.nguyen@intel.com, przemyslaw.kitszel@intel.com Errors-To: intel-wired-lan-bounces@osuosl.org Sender: "Intel-wired-lan" Instead of using shifts and casts, use FIELD_PREP after reading 40b timestamp values. Signed-off-by: Karol Kolacinski --- drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 6 ++++-- drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 13 +++++-------- 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c index 00c6483dbffc..d1b87838986d 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c @@ -1520,7 +1520,8 @@ static int ice_read_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx, * lower 8 bits in the low register, and the upper 32 bits in the high * register. */ - *tstamp = ((u64)hi) << TS_PHY_HIGH_S | ((u64)lo & TS_PHY_LOW_M); + *tstamp = FIELD_PREP(PHY_40B_HIGH_M, hi) | + FIELD_PREP(PHY_40B_LOW_M, lo); return 0; } @@ -4952,7 +4953,8 @@ ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) /* For E810 devices, the timestamp is reported with the lower 32 bits * in the low register, and the upper 8 bits in the high register. */ - *tstamp = ((u64)hi) << TS_HIGH_S | ((u64)lo & TS_LOW_M); + *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) | + FIELD_PREP(PHY_EXT_40B_LOW_M, lo); return 0; } diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h index 8a28155b206f..df94230d820f 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h @@ -673,15 +673,12 @@ static inline u64 ice_get_base_incval(struct ice_hw *hw) /* Source timer incval macros */ #define INCVAL_HIGH_M 0xFF -/* Timestamp block macros */ +/* PHY 40b registers macros */ +#define PHY_EXT_40B_LOW_M GENMASK(31, 0) +#define PHY_EXT_40B_HIGH_M GENMASK_ULL(39, 32) +#define PHY_40B_LOW_M GENMASK(7, 0) +#define PHY_40B_HIGH_M GENMASK_ULL(39, 8) #define TS_VALID BIT(0) -#define TS_LOW_M 0xFFFFFFFF -#define TS_HIGH_M 0xFF -#define TS_HIGH_S 32 - -#define TS_PHY_LOW_M 0xFF -#define TS_PHY_HIGH_M 0xFFFFFFFF -#define TS_PHY_HIGH_S 8 #define BYTES_PER_IDX_ADDR_L_U 8 #define BYTES_PER_IDX_ADDR_L 4