| Message ID | 20240808125825.560093-10-karol.kolacinski@intel.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | ice: Implement PTP support for E830 devices | expand |
On Thu, Aug 08, 2024 at 02:57:44PM +0200, Karol Kolacinski wrote: > Instead of using shifts and casts, use FIELD_PREP after reading 40b > timestamp values. > > Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> > --- > drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 6 ++++-- > drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 13 +++++-------- > 2 files changed, 9 insertions(+), 10 deletions(-) > > diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c > index 00c6483dbffc..d1b87838986d 100644 > --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c > +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c > @@ -1520,7 +1520,8 @@ static int ice_read_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx, > * lower 8 bits in the low register, and the upper 32 bits in the high > * register. > */ > - *tstamp = ((u64)hi) << TS_PHY_HIGH_S | ((u64)lo & TS_PHY_LOW_M); > + *tstamp = FIELD_PREP(PHY_40B_HIGH_M, hi) | > + FIELD_PREP(PHY_40B_LOW_M, lo); > > return 0; > } > @@ -4952,7 +4953,8 @@ ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) > /* For E810 devices, the timestamp is reported with the lower 32 bits > * in the low register, and the upper 8 bits in the high register. > */ > - *tstamp = ((u64)hi) << TS_HIGH_S | ((u64)lo & TS_LOW_M); > + *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) | > + FIELD_PREP(PHY_EXT_40B_LOW_M, lo); > > return 0; > } > diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h > index 8a28155b206f..df94230d820f 100644 > --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h > +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h > @@ -673,15 +673,12 @@ static inline u64 ice_get_base_incval(struct ice_hw *hw) > /* Source timer incval macros */ > #define INCVAL_HIGH_M 0xFF > > -/* Timestamp block macros */ > +/* PHY 40b registers macros */ > +#define PHY_EXT_40B_LOW_M GENMASK(31, 0) > +#define PHY_EXT_40B_HIGH_M GENMASK_ULL(39, 32) > +#define PHY_40B_LOW_M GENMASK(7, 0) > +#define PHY_40B_HIGH_M GENMASK_ULL(39, 8) > #define TS_VALID BIT(0) > -#define TS_LOW_M 0xFFFFFFFF > -#define TS_HIGH_M 0xFF > -#define TS_HIGH_S 32 > - > -#define TS_PHY_LOW_M 0xFF > -#define TS_PHY_HIGH_M 0xFFFFFFFF I think it it would be best to defer removing (at least) TS_PHY_LOW_M and TS_PHY_HIGH_M until the following patch, as they are still in use until then. As is, this patch results in build failures. > -#define TS_PHY_HIGH_S 8 > > #define BYTES_PER_IDX_ADDR_L_U 8 > #define BYTES_PER_IDX_ADDR_L 4 > -- > 2.45.2 > >
diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c index 00c6483dbffc..d1b87838986d 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c @@ -1520,7 +1520,8 @@ static int ice_read_ptp_tstamp_eth56g(struct ice_hw *hw, u8 port, u8 idx, * lower 8 bits in the low register, and the upper 32 bits in the high * register. */ - *tstamp = ((u64)hi) << TS_PHY_HIGH_S | ((u64)lo & TS_PHY_LOW_M); + *tstamp = FIELD_PREP(PHY_40B_HIGH_M, hi) | + FIELD_PREP(PHY_40B_LOW_M, lo); return 0; } @@ -4952,7 +4953,8 @@ ice_read_phy_tstamp_e810(struct ice_hw *hw, u8 lport, u8 idx, u64 *tstamp) /* For E810 devices, the timestamp is reported with the lower 32 bits * in the low register, and the upper 8 bits in the high register. */ - *tstamp = ((u64)hi) << TS_HIGH_S | ((u64)lo & TS_LOW_M); + *tstamp = FIELD_PREP(PHY_EXT_40B_HIGH_M, hi) | + FIELD_PREP(PHY_EXT_40B_LOW_M, lo); return 0; } diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h index 8a28155b206f..df94230d820f 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h @@ -673,15 +673,12 @@ static inline u64 ice_get_base_incval(struct ice_hw *hw) /* Source timer incval macros */ #define INCVAL_HIGH_M 0xFF -/* Timestamp block macros */ +/* PHY 40b registers macros */ +#define PHY_EXT_40B_LOW_M GENMASK(31, 0) +#define PHY_EXT_40B_HIGH_M GENMASK_ULL(39, 32) +#define PHY_40B_LOW_M GENMASK(7, 0) +#define PHY_40B_HIGH_M GENMASK_ULL(39, 8) #define TS_VALID BIT(0) -#define TS_LOW_M 0xFFFFFFFF -#define TS_HIGH_M 0xFF -#define TS_HIGH_S 32 - -#define TS_PHY_LOW_M 0xFF -#define TS_PHY_HIGH_M 0xFFFFFFFF -#define TS_PHY_HIGH_S 8 #define BYTES_PER_IDX_ADDR_L_U 8 #define BYTES_PER_IDX_ADDR_L 4
Instead of using shifts and casts, use FIELD_PREP after reading 40b timestamp values. Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> --- drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 6 ++++-- drivers/net/ethernet/intel/ice/ice_ptp_hw.h | 13 +++++-------- 2 files changed, 9 insertions(+), 10 deletions(-)