From patchwork Fri Mar 29 11:21:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Karol Kolacinski X-Patchwork-Id: 1917819 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256 header.s=default header.b=RuwDAut2; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org (client-ip=2605:bc80:3010::138; helo=smtp1.osuosl.org; envelope-from=intel-wired-lan-bounces@osuosl.org; receiver=patchwork.ozlabs.org) Received: from smtp1.osuosl.org (smtp1.osuosl.org [IPv6:2605:bc80:3010::138]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4V5dNB40R0z1yYM for ; Fri, 29 Mar 2024 22:24:26 +1100 (AEDT) Received: from localhost (localhost [127.0.0.1]) by smtp1.osuosl.org (Postfix) with ESMTP id CC60D824E2; Fri, 29 Mar 2024 11:24:20 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp1.osuosl.org ([127.0.0.1]) by localhost (smtp1.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id ECbGzVIAt5K9; Fri, 29 Mar 2024 11:24:20 +0000 (UTC) X-Comment: SPF check N/A for local connections - client-ip=140.211.166.34; helo=ash.osuosl.org; envelope-from=intel-wired-lan-bounces@osuosl.org; receiver= DKIM-Filter: OpenDKIM Filter v2.11.0 smtp1.osuosl.org 0792B82D07 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=osuosl.org; s=default; t=1711711460; bh=WStkBridNJyOTDbu+tzDPVRsF9AYP+5BMhmpN7P6L7E=; h=From:To:Date:In-Reply-To:References:Subject:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: Cc:From; b=RuwDAut2+tztTro5K7cCsjggOS/GcC1KOCZ5j/44BwRuH6O365vO6oOzdpKIUwZiA ZDJlpy+lUxNN2KkjnXL1FDhNQKEHHsVQANKC1o2ydzhvLCJAkbMy+KTRD2I64wElik nS+QFowI5taCyv9Y7gLprHS6H9GyH37odTYJwHn71tQA4nBONVQNsr5w9KKxMPOl8C 92iXYD9lKVxBMxko+/NXqapR5G5dXth5aZcFSRnI1qyD8TPwHtxZ5mLfYR04X+2E2n srzgCJgP0u+PTtxfpx1/WzF56z+Ao9bAknehcc+5d+kBXKVroTTMVapiozJw7fJeq6 uw5gTZ7QPNTXw== Received: from ash.osuosl.org (ash.osuosl.org [140.211.166.34]) by smtp1.osuosl.org (Postfix) with ESMTP id 0792B82D07; Fri, 29 Mar 2024 11:24:20 +0000 (UTC) X-Original-To: intel-wired-lan@lists.osuosl.org Delivered-To: intel-wired-lan@lists.osuosl.org Received: from smtp3.osuosl.org (smtp3.osuosl.org [140.211.166.136]) by ash.osuosl.org (Postfix) with ESMTP id 41D741BF298 for ; Fri, 29 Mar 2024 11:24:13 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by smtp3.osuosl.org (Postfix) with ESMTP id 2F04860EDE for ; Fri, 29 Mar 2024 11:24:13 +0000 (UTC) X-Virus-Scanned: amavis at osuosl.org Received: from smtp3.osuosl.org ([127.0.0.1]) by localhost (smtp3.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP id p66srOh7IsO3 for ; Fri, 29 Mar 2024 11:24:12 +0000 (UTC) Received-SPF: Pass (mailfrom) identity=mailfrom; client-ip=192.198.163.19; helo=mgamail.intel.com; envelope-from=karol.kolacinski@intel.com; receiver= DMARC-Filter: OpenDMARC Filter v1.4.2 smtp3.osuosl.org 656306067C DKIM-Filter: OpenDKIM Filter v2.11.0 smtp3.osuosl.org 656306067C Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) by smtp3.osuosl.org (Postfix) with ESMTPS id 656306067C for ; Fri, 29 Mar 2024 11:24:12 +0000 (UTC) X-CSE-ConnectionGUID: /NBht7KKRYWtl7DYv07C+g== X-CSE-MsgGUID: HN9W5edlSeGSvLCsca66Cg== X-IronPort-AV: E=McAfee;i="6600,9927,11027"; a="6755220" X-IronPort-AV: E=Sophos;i="6.07,164,1708416000"; d="scan'208";a="6755220" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Mar 2024 04:24:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.07,164,1708416000"; d="scan'208";a="16836765" Received: from kkolacin-desk1.igk.intel.com ([10.102.102.152]) by fmviesa010.fm.intel.com with ESMTP; 29 Mar 2024 04:24:10 -0700 From: Karol Kolacinski To: intel-wired-lan@lists.osuosl.org Date: Fri, 29 Mar 2024 12:21:56 +0100 Message-ID: <20240329112339.29642-26-karol.kolacinski@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240329112339.29642-14-karol.kolacinski@intel.com> References: <20240329112339.29642-14-karol.kolacinski@intel.com> MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1711711452; x=1743247452; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hwr8zz44MtuRMM9xW5X60ZXt9a7DeADvy9Wr63AH9w0=; b=K3/awHey5PdFSBAeoRTP7NYoPqVLjDlu4/nKJ+ngMP9ZfBYr/Wzacm1O 4sSUEO3mbTYhcj+61ZdHnWLSm2t2GdlcwsOf66uZJfzxaBgp/vprpoq/W 5JSwENucpa0T80XIyOkIIXlWcG2j83nNCS12m0Ap18eAOlDOSVp2JK63K y14ieGPKJaQBAhfsWrNJyy0qan+9M8eeXPg5gHWsk68RRJvX08vTZj8Lt x6gMOVoBu5A23IZfWhGg1bg+PH4QpGUbzUqnDWZjt1is1mmQAZ9enR+j4 8tfM6RZAuM5rdoGueqtGDqfGkmt1hl+2FG37GOfUB4LQiy9d19hZlKO16 A==; X-Mailman-Original-Authentication-Results: smtp3.osuosl.org; dmarc=pass (p=none dis=none) header.from=intel.com X-Mailman-Original-Authentication-Results: smtp3.osuosl.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=K3/awHey Subject: [Intel-wired-lan] [PATCH v3 iwl-next 12/12] ice: Adjust PTP init for 2x50G E825C devices X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: netdev@vger.kernel.org, Arkadiusz Kubalewski , Karol Kolacinski , anthony.l.nguyen@intel.com Errors-To: intel-wired-lan-bounces@osuosl.org Sender: "Intel-wired-lan" From: Grzegorz Nitka From FW/HW perspective, 2 port topology in E825C devices requires merging of 2 port mapping internally to CPK and breakout mapping externally to CPK. As a consequence, it requires different port numbering from PTP code perspective. For that topology, pf_id can not be used to index PTP ports. Even if the 2nd port is identified as port with pf_id = 1, all PHY operations need to be performed as it was port 2. Thus, special mapping is needed for the 2nd port. This change adds detection of 2x50G topology and applies 'custom' mapping on the 2nd port. Signed-off-by: Grzegorz Nitka Reviewed-by: Arkadiusz Kubalewski Signed-off-by: Karol Kolacinski --- .../net/ethernet/intel/ice/ice_hw_autogen.h | 4 ++++ drivers/net/ethernet/intel/ice/ice_ptp.c | 5 ++++ drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 23 +++++++++++++++++++ drivers/net/ethernet/intel/ice/ice_type.h | 9 ++++++++ 4 files changed, 41 insertions(+) diff --git a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h index cfac1d432c15..26260eed852d 100644 --- a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h +++ b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h @@ -157,6 +157,8 @@ #define GLGEN_RTRIG_CORER_M BIT(0) #define GLGEN_RTRIG_GLOBR_M BIT(1) #define GLGEN_STAT 0x000B612C +#define GLGEN_SWITCH_MODE_CONFIG 0x000B81E0 +#define GLGEN_SWITCH_MODE_CONFIG_SELECT_25X4_ON_SINGLE_QUAD_M BIT(2) #define GLGEN_VFLRSTAT(_i) (0x00093A04 + ((_i) * 4)) #define PFGEN_CTRL 0x00091000 #define PFGEN_CTRL_PFSWR_M BIT(0) @@ -177,6 +179,8 @@ #define GLINT_CTL_ITR_GRAN_50_M ICE_M(0xF, 24) #define GLINT_CTL_ITR_GRAN_25_S 28 #define GLINT_CTL_ITR_GRAN_25_M ICE_M(0xF, 28) +#define GLGEN_MAC_LINK_TOPO 0x000B81DC +#define GLGEN_MAC_LINK_TOPO_LINK_TOPO_M GENMASK(1, 0) #define GLINT_DYN_CTL(_INT) (0x00160000 + ((_INT) * 4)) #define GLINT_DYN_CTL_INTENA_M BIT(0) #define GLINT_DYN_CTL_CLEARPBA_M BIT(1) diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c index 811830eab385..73898aa08dc5 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp.c @@ -1472,6 +1472,8 @@ void ice_ptp_link_change(struct ice_pf *pf, u8 port, bool linkup) return; ptp_port = &pf->ptp.port; + if (ice_is_e825c(hw) && hw->ptp.is_2x50g_muxed_topo) + port *= 2; if (WARN_ON_ONCE(ptp_port->port_num != port)) return; @@ -3329,6 +3331,9 @@ void ice_ptp_init(struct ice_pf *pf) } ptp->port.port_num = hw->pf_id; + if (ice_is_e825c(hw) && hw->ptp.is_2x50g_muxed_topo) + ptp->port.port_num = hw->pf_id * 2; + err = ice_ptp_init_port(pf, &ptp->port); if (err) goto err; diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c index 49c289e792f4..22b537554748 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c @@ -2469,6 +2469,27 @@ static int ice_get_phy_tx_tstamp_ready_eth56g(struct ice_hw *hw, u8 port, return 0; } +/** + * ice_is_muxed_topo - detect breakout 2x50G topology for E825C + * @hw: pointer to the HW struct + * + * Returns: true if it's 2x50 breakout topology, false otherwise + */ +static bool ice_is_muxed_topo(struct ice_hw *hw) +{ + u8 link_topo; + bool mux; + u32 val; + + val = rd32(hw, GLGEN_SWITCH_MODE_CONFIG); + mux = FIELD_GET(GLGEN_SWITCH_MODE_CONFIG_SELECT_25X4_ON_SINGLE_QUAD_M, + val); + val = rd32(hw, GLGEN_MAC_LINK_TOPO); + link_topo = FIELD_GET(GLGEN_MAC_LINK_TOPO_LINK_TOPO_M, val); + + return (mux && link_topo == ICE_LINK_TOPO_UP_TO_2_LINKS); +} + /** * ice_ptp_init_phy_e825c - initialize PHY parameters * @hw: pointer to the HW struct @@ -2501,6 +2522,8 @@ static void ice_ptp_init_phy_e825c(struct ice_hw *hw) return; } } + + ptp->is_2x50g_muxed_topo = ice_is_muxed_topo(hw); } /* E822 family functions diff --git a/drivers/net/ethernet/intel/ice/ice_type.h b/drivers/net/ethernet/intel/ice/ice_type.h index e019dad56819..c5b2ad113d1a 100644 --- a/drivers/net/ethernet/intel/ice/ice_type.h +++ b/drivers/net/ethernet/intel/ice/ice_type.h @@ -851,6 +851,14 @@ enum ice_phy_model { ICE_PHY_ETH56G, }; +/* Global Link Topology */ +enum ice_global_link_topo { + ICE_LINK_TOPO_UP_TO_2_LINKS, + ICE_LINK_TOPO_UP_TO_4_LINKS, + ICE_LINK_TOPO_UP_TO_8_LINKS, + ICE_LINK_TOPO_RESERVED, +}; + struct ice_ptp_hw { enum ice_phy_model phy_model; union ice_phy_params phy; @@ -858,6 +866,7 @@ struct ice_ptp_hw { u8 ports_per_phy; bool primary_nac; struct ice_hw *primary_hw; + bool is_2x50g_muxed_topo; }; /* Port hardware description */