| Message ID | 20230802061946.3489037-1-sasha.neftin@intel.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [iwl-net,v1,1/1] igc: Fix the typo in the PTM Control macro | expand |
Dear Sasha, Thank you for your patch. Am 02.08.23 um 08:19 schrieb Sasha Neftin: > The IGC_PTM_CTRL_SHRT_CYC defined the time between two consecutive PTM define*s* > requests. The bit resolution of this field is six bits. This patch comes > to correct the typo in the IGC_PTM_CTRL_SHRT_CYC macro. Well bit six was set before, wasn’t it? If you resend, you can write, that bit five was missing in the mask. For the summary I suggest something like: igc: Also set bit 5 in mask in PTM Control macro > Fixes: a90ec8483732 ("igc: Add support for PTP getcrosststamp()") > Signed-off-by: Sasha Neftin <sasha.neftin@intel.com> > --- > drivers/net/ethernet/intel/igc/igc_defines.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/net/ethernet/intel/igc/igc_defines.h b/drivers/net/ethernet/intel/igc/igc_defines.h > index c3722f524ea7..0bac6eeb42c0 100644 > --- a/drivers/net/ethernet/intel/igc/igc_defines.h > +++ b/drivers/net/ethernet/intel/igc/igc_defines.h > @@ -546,7 +546,7 @@ > #define IGC_PTM_CTRL_START_NOW BIT(29) /* Start PTM Now */ > #define IGC_PTM_CTRL_EN BIT(30) /* Enable PTM */ > #define IGC_PTM_CTRL_TRIG BIT(31) /* PTM Cycle trigger */ > -#define IGC_PTM_CTRL_SHRT_CYC(usec) (((usec) & 0x2f) << 2) > +#define IGC_PTM_CTRL_SHRT_CYC(usec) (((usec) & 0x3f) << 2) > #define IGC_PTM_CTRL_PTM_TO(usec) (((usec) & 0xff) << 8) > > #define IGC_PTM_SHORT_CYC_DEFAULT 1 /* Default short cycle interval */ Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de> Kind regards, Paul
diff --git a/drivers/net/ethernet/intel/igc/igc_defines.h b/drivers/net/ethernet/intel/igc/igc_defines.h index c3722f524ea7..0bac6eeb42c0 100644 --- a/drivers/net/ethernet/intel/igc/igc_defines.h +++ b/drivers/net/ethernet/intel/igc/igc_defines.h @@ -546,7 +546,7 @@ #define IGC_PTM_CTRL_START_NOW BIT(29) /* Start PTM Now */ #define IGC_PTM_CTRL_EN BIT(30) /* Enable PTM */ #define IGC_PTM_CTRL_TRIG BIT(31) /* PTM Cycle trigger */ -#define IGC_PTM_CTRL_SHRT_CYC(usec) (((usec) & 0x2f) << 2) +#define IGC_PTM_CTRL_SHRT_CYC(usec) (((usec) & 0x3f) << 2) #define IGC_PTM_CTRL_PTM_TO(usec) (((usec) & 0xff) << 8) #define IGC_PTM_SHORT_CYC_DEFAULT 1 /* Default short cycle interval */
The IGC_PTM_CTRL_SHRT_CYC defined the time between two consecutive PTM requests. The bit resolution of this field is six bits. This patch comes to correct the typo in the IGC_PTM_CTRL_SHRT_CYC macro. Fixes: a90ec8483732 ("igc: Add support for PTP getcrosststamp()") Signed-off-by: Sasha Neftin <sasha.neftin@intel.com> --- drivers/net/ethernet/intel/igc/igc_defines.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)