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Thu, 23 Feb 2023 07:03:50 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6500,9779,10629"; a="360624606" X-IronPort-AV: E=Sophos;i="5.97,320,1669104000"; d="scan'208";a="360624606" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Feb 2023 23:03:28 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10629"; a="796193429" X-IronPort-AV: E=Sophos;i="5.97,320,1669104000"; d="scan'208";a="796193429" Received: from ccdlinuxdev11.iil.intel.com ([143.185.162.129]) by orsmga004.jf.intel.com with ESMTP; 22 Feb 2023 23:03:21 -0800 From: Sasha Neftin To: intel-wired-lan@lists.osuosl.org Date: Thu, 23 Feb 2023 09:03:17 +0200 Message-Id: <20230223070317.3258883-1-sasha.neftin@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1677135830; x=1708671830; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=thzpsDGNcUxZ+piStdfWHdvEhkTNSB/KsIEko13gzcE=; b=EQ9TI1+dwJ2lGbuUkUoWKdZ2H/8tLnSoqpATMj5WH//xLW9GL371Zy8q 4z1x6OAqTWkk2nFA0O1T3KKQsp4JqaGGiT1uRnqD3joXE9qtzAZ6sAIir rs5h4r311AvkMuCXKRSq6jbCLJY7xfCT0Ka3a0rNTL4UXHl9pyZlQ0olD YgUv8yhX2UiLrKq1ixzqubZ6MkGQnJrsMnkBDSV7f/w7rNV54stWPsclo xLGS/baSacSxs8BmQXYTN4kY1fyi8vL0YoeNrwPh7v2JXpFALuCXpVCxZ aS7JPi8miEY01PPqswUJ5sy/3Ho2yP+apazvltDC5du3cUiX2ckQ26gvR Q==; X-Mailman-Original-Authentication-Results: smtp1.osuosl.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=EQ9TI1+d Subject: [Intel-wired-lan] [PATCH v1 1/1] igc: Remove obsolete DMA coalescing code X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-wired-lan-bounces@osuosl.org Sender: "Intel-wired-lan" DMA coalescing is not applicable for i225 parts. This patch comes to tidy up the driver code. Signed-off-by: Sasha Neftin Tested-by: Naama Meir --- drivers/net/ethernet/intel/igc/igc_defines.h | 3 --- drivers/net/ethernet/intel/igc/igc_i225.c | 19 +++++-------------- drivers/net/ethernet/intel/igc/igc_regs.h | 1 - 3 files changed, 5 insertions(+), 18 deletions(-) diff --git a/drivers/net/ethernet/intel/igc/igc_defines.h b/drivers/net/ethernet/intel/igc/igc_defines.h index 9dec3563ce3a..44a507029946 100644 --- a/drivers/net/ethernet/intel/igc/igc_defines.h +++ b/drivers/net/ethernet/intel/igc/igc_defines.h @@ -662,9 +662,6 @@ */ #define IGC_TW_SYSTEM_100_MASK 0x0000FF00 #define IGC_TW_SYSTEM_100_SHIFT 8 -#define IGC_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */ -#define IGC_DMACR_DMACTHR_MASK 0x00FF0000 -#define IGC_DMACR_DMACTHR_SHIFT 16 /* Reg val to set scale to 1024 nsec */ #define IGC_LTRMINV_SCALE_1024 2 /* Reg val to set scale to 32768 nsec */ diff --git a/drivers/net/ethernet/intel/igc/igc_i225.c b/drivers/net/ethernet/intel/igc/igc_i225.c index 59d5c467ea6e..17546a035ab1 100644 --- a/drivers/net/ethernet/intel/igc/igc_i225.c +++ b/drivers/net/ethernet/intel/igc/igc_i225.c @@ -593,20 +593,11 @@ s32 igc_set_ltr_i225(struct igc_hw *hw, bool link) size = rd32(IGC_RXPBS) & IGC_RXPBS_SIZE_I225_MASK; - /* Calculations vary based on DMAC settings. */ - if (rd32(IGC_DMACR) & IGC_DMACR_DMAC_EN) { - size -= (rd32(IGC_DMACR) & - IGC_DMACR_DMACTHR_MASK) >> - IGC_DMACR_DMACTHR_SHIFT; - /* Convert size to bits. */ - size *= 1024 * 8; - } else { - /* Convert size to bytes, subtract the MTU, and then - * convert the size to bits. - */ - size *= 1024; - size *= 8; - } + /* Convert size to bytes, subtract the MTU, and then + * convert the size to bits. + */ + size *= 1024; + size *= 8; if (size < 0) { hw_dbg("Invalid effective Rx buffer size %d\n", diff --git a/drivers/net/ethernet/intel/igc/igc_regs.h b/drivers/net/ethernet/intel/igc/igc_regs.h index 01c86d36856d..dba5a5759b1c 100644 --- a/drivers/net/ethernet/intel/igc/igc_regs.h +++ b/drivers/net/ethernet/intel/igc/igc_regs.h @@ -292,7 +292,6 @@ /* LTR registers */ #define IGC_LTRC 0x01A0 /* Latency Tolerance Reporting Control */ -#define IGC_DMACR 0x02508 /* DMA Coalescing Control Register */ #define IGC_LTRMINV 0x5BB0 /* LTR Minimum Value */ #define IGC_LTRMAXV 0x5BB4 /* LTR Maximum Value */