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Fri, 9 Dec 2022 04:18:13 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6500,9779,10555"; a="300796344" X-IronPort-AV: E=Sophos;i="5.96,230,1665471600"; d="scan'208";a="300796344" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Dec 2022 20:18:13 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10555"; a="649427546" X-IronPort-AV: E=Sophos;i="5.96,230,1665471600"; d="scan'208";a="649427546" Received: from zulkifl3-ilbpg0.png.intel.com ([10.88.229.82]) by fmsmga007.fm.intel.com with ESMTP; 08 Dec 2022 20:18:11 -0800 From: Muhammad Husaini Zulkifli To: intel-wired-lan@osuosl.org, vinicius.gomes@intel.com Date: Fri, 9 Dec 2022 12:15:21 +0800 Message-Id: <20221209041522.30153-6-muhammad.husaini.zulkifli@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221209041522.30153-1-muhammad.husaini.zulkifli@intel.com> References: <20221209041522.30153-1-muhammad.husaini.zulkifli@intel.com> X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670559493; x=1702095493; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=VNveEnedm9541A1azAGeWzcSPFecWOHczVu1Cej2fY0=; b=C6CKzYOyInwnHPmWZbvZuZblGEEc2P1k4VX0wO6kIpNXZXJgAQB4finX CwskIBJT9f/vPTcVRT4QIUl20AF9zXQDZen0VfIPKRjAH4wY9CusH0A9I YLQfO8FKnK/4qP4bN++n3hQGwUN39KwqGxmrUYwGLwEtPxx4ZIrIJlSqs J90r9heAIljsU4MdBIwfmAuO+U3qfFmi2hZJsakKN8LTIdjqF3VCWYB4s nP7U/AalI8X2eEtG6HtyXpN3Zxbsy59x07gkqPi04VwjiAlBBEAlif++4 JRgkXtSb/psBIwZTVlBXKfDkuTBw0jLXgBOAU6V75Hbb+6rN/EmbZvARo A==; X-Mailman-Original-Authentication-Results: smtp1.osuosl.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=C6CKzYOy Subject: [Intel-wired-lan] [PATCH net v1 5/6] igc: recalculate Qbv end_time by considering cycle time X-BeenThere: intel-wired-lan@osuosl.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: muhammad.husaini.zulkifli@intel.com, anthony.l.nguyen@intel.com, tee.min.tan@linux.intel.com MIME-Version: 1.0 Errors-To: intel-wired-lan-bounces@osuosl.org Sender: "Intel-wired-lan" From: Tan Tee Min Qbv users can specify a cycle time that is not equal to the total GCL intervals. Hence, recalculation is necessary here to exclude the time interval that exceeds the cycle time. As those GCL which exceeds the cycle time will be truncated. According to IEEE Std. 802.1Q-2018 section 8.6.9.2, once the end of the list is reached, it will switch to the END_OF_CYCLE state and leave the gates in the same state until the next cycle is started. Fixes: ec50a9d437f0 ("igc: Add support for taprio offloading") Signed-off-by: Tan Tee Min Signed-off-by: Muhammad Husaini Zulkifli --- drivers/net/ethernet/intel/igc/igc_main.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/net/ethernet/intel/igc/igc_main.c b/drivers/net/ethernet/intel/igc/igc_main.c index 6a95718bd575..5f1c272511fd 100644 --- a/drivers/net/ethernet/intel/igc/igc_main.c +++ b/drivers/net/ethernet/intel/igc/igc_main.c @@ -6050,6 +6050,21 @@ static int igc_save_qbv_schedule(struct igc_adapter *adapter, end_time += e->interval; + /* If any of the conditions below are true, we need to manually + * control the end time of the cycle. + * 1. Qbv users can specify a cycle time that is not equal + * to the total GCL intervals. Hence, recalculation is + * necessary here to exclude the time interval that + * exceeds the cycle time. + * 2. According to IEEE Std. 802.1Q-2018 section 8.6.9.2, + * once the end of the list is reached, it will switch + * to the END_OF_CYCLE state and leave the gates in the + * same state until the next cycle is started. + */ + if (end_time > adapter->cycle_time || + n + 1 == qopt->num_entries) + end_time = adapter->cycle_time; + for (i = 0; i < adapter->num_tx_queues; i++) { struct igc_ring *ring = adapter->tx_ring[i];