diff mbox

[next,S28,09/15] i40e: Do not disable queues in the Legacy/MSI Interrupt handler

Message ID 1452897202-15204-10-git-send-email-joshua.a.hay@intel.com
State Accepted
Delegated to: Jeff Kirsher
Headers show

Commit Message

Joshua Hay Jan. 15, 2016, 10:33 p.m. UTC
From: Anjali Singhai Jain <anjali.singhai@intel.com>

The queues should never be enabled/disabled in the interrupt handler,
ICR0 interrupt enable should be the only thing that needs to be
dynamically changed in the handler.

This patch fixes that. Without this patch X722 platforms were
seeing weird ping timings when in Legacy mode since it takes
a whole lot of time for the HW/FW to re-enable queues.

Signed-off-by: Anjali Singhai Jain <anjali.singhai@intel.com>
Change-ID: If065afc45d81c5a19d4a94a00cd5b8f61cefc40c
---
Testing Hints (Required if no HSD): Test with legacy mode
enabled.

 drivers/net/ethernet/intel/i40e/i40e_main.c | 16 ++++++----------
 drivers/net/ethernet/intel/i40e/i40e_txrx.c | 13 -------------
 2 files changed, 6 insertions(+), 23 deletions(-)

Comments

Bowers, AndrewX Jan. 27, 2016, 8:29 p.m. UTC | #1
> -----Original Message-----
> From: Intel-wired-lan [mailto:intel-wired-lan-bounces@lists.osuosl.org] On
> Behalf Of Joshua Hay
> Sent: Friday, January 15, 2016 2:33 PM
> To: intel-wired-lan@lists.osuosl.org
> Subject: [Intel-wired-lan] [next PATCH S28 09/15] i40e: Do not disable
> queues in the Legacy/MSI Interrupt handler
> 
> From: Anjali Singhai Jain <anjali.singhai@intel.com>
> 
> The queues should never be enabled/disabled in the interrupt handler,
> ICR0 interrupt enable should be the only thing that needs to be dynamically
> changed in the handler.
> 
> This patch fixes that. Without this patch X722 platforms were seeing weird
> ping timings when in Legacy mode since it takes a whole lot of time for the
> HW/FW to re-enable queues.
> 
> Signed-off-by: Anjali Singhai Jain <anjali.singhai@intel.com>
> Change-ID: If065afc45d81c5a19d4a94a00cd5b8f61cefc40c
> ---
> Testing Hints (Required if no HSD): Test with legacy mode enabled.
> 
>  drivers/net/ethernet/intel/i40e/i40e_main.c | 16 ++++++----------
> drivers/net/ethernet/intel/i40e/i40e_txrx.c | 13 -------------
>  2 files changed, 6 insertions(+), 23 deletions(-)

Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Patch code changes correctly applied, ping times normal/consistent on X722 in Legacy mode
diff mbox

Patch

diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c
index 90e37f4..5e7a7a1 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_main.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_main.c
@@ -3462,16 +3462,12 @@  static irqreturn_t i40e_intr(int irq, void *data)
 		struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
 		struct i40e_q_vector *q_vector = vsi->q_vectors[0];
 
-		/* temporarily disable queue cause for NAPI processing */
-		u32 qval = rd32(hw, I40E_QINT_RQCTL(0));
-
-		qval &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
-		wr32(hw, I40E_QINT_RQCTL(0), qval);
-
-		qval = rd32(hw, I40E_QINT_TQCTL(0));
-		qval &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
-		wr32(hw, I40E_QINT_TQCTL(0), qval);
-
+		/* We do not have a way to disarm Queue causes while leaving
+		 * interrupt enabled for all other causes, ideally
+		 * interrupt should be disabled while we are in NAPI but
+		 * this is not a performance path and napi_schedule()
+		 * can deal with rescheduling.
+		 */
 		if (!test_bit(__I40E_DOWN, &pf->state))
 			napi_schedule_irqoff(&q_vector->napi);
 	}
diff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.c b/drivers/net/ethernet/intel/i40e/i40e_txrx.c
index cd9bb7f..61e98f5 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_txrx.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.c
@@ -2051,19 +2051,6 @@  tx_only:
 	if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
 		i40e_update_enable_itr(vsi, q_vector);
 	} else { /* Legacy mode */
-		struct i40e_hw *hw = &vsi->back->hw;
-		/* We re-enable the queue 0 cause, but
-		 * don't worry about dynamic_enable
-		 * because we left it on for the other
-		 * possible interrupts during napi
-		 */
-		u32 qval = rd32(hw, I40E_QINT_RQCTL(0)) |
-			   I40E_QINT_RQCTL_CAUSE_ENA_MASK;
-
-		wr32(hw, I40E_QINT_RQCTL(0), qval);
-		qval = rd32(hw, I40E_QINT_TQCTL(0)) |
-		       I40E_QINT_TQCTL_CAUSE_ENA_MASK;
-		wr32(hw, I40E_QINT_TQCTL(0), qval);
 		i40e_irq_dynamic_enable_icr0(vsi->back, false);
 	}
 	return 0;