From patchwork Thu Apr 30 18:19:15 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Harvey X-Patchwork-Id: 466690 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from hemlock.osuosl.org (hemlock.osuosl.org [140.211.166.133]) by ozlabs.org (Postfix) with ESMTP id 6706B140310 for ; Fri, 1 May 2015 04:27:09 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by hemlock.osuosl.org (Postfix) with ESMTP id AE38B95F26; Thu, 30 Apr 2015 18:27:08 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from hemlock.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id z53uCytWV-xY; Thu, 30 Apr 2015 18:27:08 +0000 (UTC) Received: from ash.osuosl.org (ash.osuosl.org [140.211.166.34]) by hemlock.osuosl.org (Postfix) with ESMTP id EF8C295F1D; Thu, 30 Apr 2015 18:27:07 +0000 (UTC) X-Original-To: intel-wired-lan@lists.osuosl.org Delivered-To: intel-wired-lan@lists.osuosl.org Received: from whitealder.osuosl.org (whitealder.osuosl.org [140.211.166.138]) by ash.osuosl.org (Postfix) with ESMTP id 5E96B1BFA96 for ; Thu, 30 Apr 2015 18:27:07 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by whitealder.osuosl.org (Postfix) with ESMTP id 57F3691AE6 for ; Thu, 30 Apr 2015 18:27:07 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from whitealder.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id t-nUVPzYrE6K for ; Thu, 30 Apr 2015 18:27:06 +0000 (UTC) X-Greylist: delayed 00:07:42 by SQLgrey-1.7.6 Received: from mail-pa0-f54.google.com (mail-pa0-f54.google.com [209.85.220.54]) by whitealder.osuosl.org (Postfix) with ESMTPS id 80CF491AE8 for ; Thu, 30 Apr 2015 18:27:06 +0000 (UTC) Received: by pacyx8 with SMTP id yx8so67367445pac.1 for ; Thu, 30 Apr 2015 11:27:06 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Jfw74cihJlH9ZVJneQWc2LZWz6qP1qz7O1eUHCgxYDU=; b=KpCKEeFP/KDqsKQs3A6A7Un/uI/O4SXICEtzOvmUGKTs6DmHTWgnnrEvI/nK4qG1UV WB3VFmC7+B9GoGU8jot0cPxD3pxiJoXChLYNklFRetEonAO7h5Ql4UTNNdGBrbqNbdNB xM4khzI/1WNsUScOPj86wVD/OgiIG5ywZemx7W/Li6QYt8TZDM/Yr8HLuGXXrpJ/D5hZ Djb3x05MWJn7x3uXKMyskdn7cdXb3YCFZczTlGNBLd22OOXDiu5y04tX4FKGuJchsQ8q hfa1oQw+Ed/1HmGh6NAVI0ogw7vp8ENcI8K5+D+z2F0emNHO2r8UPZSQ3ultoyN/p04R VTqg== X-Gm-Message-State: ALoCoQktXBYC1lGLNmaAMnGzzJXb9wJeP/OEaX1sMBxVXSXqlI70eEHGyKbFwLKO5a52kuKpZpRP X-Received: by 10.70.136.1 with SMTP id pw1mr10509570pdb.21.1430417964468; Thu, 30 Apr 2015 11:19:24 -0700 (PDT) Received: from tharvey.gw (68-189-91-139.static.snlo.ca.charter.com. [68.189.91.139]) by mx.google.com with ESMTPSA id bs4sm2821374pdb.21.2015.04.30.11.19.23 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 30 Apr 2015 11:19:23 -0700 (PDT) From: Tim Harvey To: Jeff Kirsher Date: Thu, 30 Apr 2015 11:19:15 -0700 Message-Id: <1430417955-28252-4-git-send-email-tharvey@gateworks.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1430417955-28252-1-git-send-email-tharvey@gateworks.com> References: <1430417955-28252-1-git-send-email-tharvey@gateworks.com> Cc: intel-wired-lan@lists.osuosl.org Subject: [Intel-wired-lan] [PATCH 3/3] net: igb: register mii_bus for SerDes w/ external phy X-BeenThere: intel-wired-lan@lists.osuosl.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-wired-lan-bounces@lists.osuosl.org Sender: "Intel-wired-lan" If an i210 is configured for 1000BASE-BX link_mode and has an external phy specified, then register an mii bus using the external phy address as a mask. An i210 hooked to an external standard phy will be configured with a link_mode of SGMII in which case phy ops will be configured and used internal in the igb driver for link status. However, in certain cases one might be using a backplane SerDes connection to something that talks on the mdio bus but is not a standard phy, such as a switch. In this case by registering an mdio bus a phy driver can manage the device. Signed-off-by: Tim Harvey --- drivers/net/ethernet/intel/igb/e1000_82575.c | 16 +++ drivers/net/ethernet/intel/igb/e1000_hw.h | 7 ++ drivers/net/ethernet/intel/igb/igb_main.c | 163 ++++++++++++++++++++++++++- 3 files changed, 181 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/intel/igb/e1000_82575.c b/drivers/net/ethernet/intel/igb/e1000_82575.c index d2afd7b..e80617b 100644 --- a/drivers/net/ethernet/intel/igb/e1000_82575.c +++ b/drivers/net/ethernet/intel/igb/e1000_82575.c @@ -598,13 +598,26 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw) switch (link_mode) { case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: hw->phy.media_type = e1000_media_type_internal_serdes; + if (igb_sgmii_uses_mdio_82575(hw)) { + u32 mdicnfg = rd32(E1000_MDICNFG); + + mdicnfg &= E1000_MDICNFG_PHY_MASK; + hw->phy.addr = mdicnfg >> E1000_MDICNFG_PHY_SHIFT; + hw_dbg("1000BASE_KX w/ external MDIO device at 0x%x\n", + hw->phy.addr); + } else { + hw_dbg("1000BASE_KX"); + } break; case E1000_CTRL_EXT_LINK_MODE_SGMII: /* Get phy control interface type set (MDIO vs. I2C)*/ if (igb_sgmii_uses_mdio_82575(hw)) { hw->phy.media_type = e1000_media_type_copper; dev_spec->sgmii_active = true; + hw_dbg("SGMII with external MDIO PHY"); break; + } else { + hw_dbg("SGMII with external I2C PHY"); } /* fall through for I2C based SGMII */ case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: @@ -621,8 +634,11 @@ static s32 igb_get_invariants_82575(struct e1000_hw *hw) hw->phy.media_type = e1000_media_type_copper; dev_spec->sgmii_active = true; } + hw_dbg("SERDES with external SFP"); break; + } else { + hw_dbg("SERDES"); } /* do not change link mode for 100BaseFX */ diff --git a/drivers/net/ethernet/intel/igb/e1000_hw.h b/drivers/net/ethernet/intel/igb/e1000_hw.h index 2003b37..2864779 100644 --- a/drivers/net/ethernet/intel/igb/e1000_hw.h +++ b/drivers/net/ethernet/intel/igb/e1000_hw.h @@ -27,6 +27,7 @@ #include #include #include +#include #include "e1000_regs.h" #include "e1000_defines.h" @@ -543,6 +544,12 @@ struct e1000_hw { struct e1000_mbx_info mbx; struct e1000_host_mng_dhcp_cookie mng_cookie; +#ifdef CONFIG_PHYLIB + /* Phylib and MDIO interface */ + struct mii_bus *mii_bus; + struct phy_device *phy_dev; + phy_interface_t phy_interface; +#endif union { struct e1000_dev_spec_82575 _82575; } dev_spec; diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c index f366b3b..9b5f538 100644 --- a/drivers/net/ethernet/intel/igb/igb_main.c +++ b/drivers/net/ethernet/intel/igb/igb_main.c @@ -41,6 +41,7 @@ #include #include #include +#include #include #include #include @@ -2223,6 +2224,121 @@ static s32 igb_init_i2c(struct igb_adapter *adapter) return status; } +#ifdef CONFIG_PHYLIB +static int igb_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) +{ + struct e1000_hw *hw = bus->priv; + u16 out; + int err; + + err = igb_read_reg_gs40g(hw, mii_id, regnum, &out); + if (err) + return err; + return out; +} + +static int igb_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, + u16 val) +{ + struct e1000_hw *hw = bus->priv; + + return igb_write_reg_gs40g(hw, mii_id, regnum, val); +} + +static int igb_enet_mdio_reset(struct mii_bus *bus) +{ + usleep_range(1000, 2000); + return 0; +} + +static void igb_enet_mii_link(struct net_device *netdev) +{ +} + +/* Probe the mdio bus for phys and connect them */ +static int igb_enet_mii_probe(struct net_device *netdev) +{ + struct igb_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; + struct phy_device *phy_dev = NULL; + int phy_id; + + /* check for attached phy */ + for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { + if (hw->mii_bus->phy_map[phy_id]) { + phy_dev = hw->mii_bus->phy_map[phy_id]; + break; + } + } + if (!phy_dev) { + netdev_err(netdev, "no PHY found\n"); + return -ENODEV; + } + + hw->phy_interface = PHY_INTERFACE_MODE_RGMII; + phy_dev = phy_connect(netdev, dev_name(&phy_dev->dev), + igb_enet_mii_link, hw->phy_interface); + if (IS_ERR(phy_dev)) { + netdev_err(netdev, "could not attach to PHY\n"); + return PTR_ERR(phy_dev); + } + + hw->phy_dev = phy_dev; + netdev_info(netdev, "igb PHY driver [%s] (mii_bus:phy_addr=%s)\n", + hw->phy_dev->drv->name, dev_name(&hw->phy_dev->dev)); + + return 0; +} + +/* Create and register mdio bus */ +static int igb_enet_mii_init(struct pci_dev *pdev) +{ + struct mii_bus *mii_bus; + struct net_device *netdev = pci_get_drvdata(pdev); + struct igb_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; + int err; + + mii_bus = mdiobus_alloc(); + if (!mii_bus) { + err = -ENOMEM; + goto err_out; + } + + mii_bus->name = "igb_enet_mii_bus"; + mii_bus->read = igb_enet_mdio_read; + mii_bus->write = igb_enet_mdio_write; + mii_bus->reset = igb_enet_mdio_reset; + snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", + pci_name(pdev), hw->device_id + 1); + mii_bus->priv = hw; + mii_bus->parent = &pdev->dev; + mii_bus->phy_mask = ~(1 << hw->phy.addr); + + err = mdiobus_register(mii_bus); + if (err) { + netdev_err(netdev, "failed to register mii_bus: %d\n", err); + goto err_out_free_mdiobus; + } + hw->mii_bus = mii_bus; + + return 0; + +err_out_free_mdiobus: + mdiobus_free(mii_bus); +err_out: + return err; +} + +static void igb_enet_mii_remove(struct e1000_hw *hw) +{ + if (hw->mii_bus) { + mdiobus_unregister(hw->mii_bus); + mdiobus_free(hw->mii_bus); + } +} +#endif /* CONFIG_PHYLIB */ + /** * igb_probe - Device Initialization Routine * @pdev: PCI device information struct @@ -2645,6 +2761,13 @@ static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) } } pm_runtime_put_noidle(&pdev->dev); + +#ifdef CONFIG_PHYLIB + /* create and register the mdio bus if using ext phy */ + if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO) + igb_enet_mii_init(pdev); +#endif + return 0; err_register: @@ -2788,6 +2911,10 @@ static void igb_remove(struct pci_dev *pdev) struct e1000_hw *hw = &adapter->hw; pm_runtime_get_noresume(&pdev->dev); +#ifdef CONFIG_PHYLIB + if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO) + igb_enet_mii_remove(hw); +#endif #ifdef CONFIG_IGB_HWMON igb_sysfs_exit(adapter); #endif @@ -3093,6 +3220,12 @@ static int __igb_open(struct net_device *netdev, bool resuming) if (!resuming) pm_runtime_put(&pdev->dev); +#ifdef CONFIG_PHYLIB + /* Probe and connect to PHY if using ext phy */ + if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO) + igb_enet_mii_probe(netdev); +#endif + /* start the watchdog. */ hw->mac.get_link_status = 1; schedule_work(&adapter->watchdog_task); @@ -7127,21 +7260,41 @@ void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) { struct igb_adapter *adapter = netdev_priv(netdev); + struct e1000_hw *hw = &adapter->hw; struct mii_ioctl_data *data = if_mii(ifr); - if (adapter->hw.phy.media_type != e1000_media_type_copper) + if (adapter->hw.phy.media_type != e1000_media_type_copper && + !(rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO)) return -EOPNOTSUPP; switch (cmd) { case SIOCGMIIPHY: - data->phy_id = adapter->hw.phy.addr; + data->phy_id = hw->phy.addr; break; case SIOCGMIIREG: - if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, - &data->val_out)) - return -EIO; + if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) { + if (igb_read_reg_gs40g(&adapter->hw, data->phy_id, + data->reg_num & 0x1F, + &data->val_out)) + return -EIO; + } else { + if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, + &data->val_out)) + return -EIO; + } break; case SIOCSMIIREG: + if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) { + if (igb_write_reg_gs40g(hw, data->phy_id, + data->reg_num & 0x1F, + data->val_in)) + return -EIO; + } else { + if (igb_write_phy_reg(hw, data->reg_num & 0x1F, + data->val_in)) + return -EIO; + } + break; default: return -EOPNOTSUPP; }