From patchwork Thu Apr 30 18:19:13 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Harvey X-Patchwork-Id: 466687 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from whitealder.osuosl.org (whitealder.osuosl.org [140.211.166.138]) by ozlabs.org (Postfix) with ESMTP id 59E5A140323 for ; Fri, 1 May 2015 04:24:49 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by whitealder.osuosl.org (Postfix) with ESMTP id 75F5E91ADE; Thu, 30 Apr 2015 18:24:48 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from whitealder.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ZluZtGBgn18z; Thu, 30 Apr 2015 18:24:47 +0000 (UTC) Received: from ash.osuosl.org (ash.osuosl.org [140.211.166.34]) by whitealder.osuosl.org (Postfix) with ESMTP id EB4F0919DE; Thu, 30 Apr 2015 18:24:47 +0000 (UTC) X-Original-To: intel-wired-lan@lists.osuosl.org Delivered-To: intel-wired-lan@lists.osuosl.org Received: from whitealder.osuosl.org (whitealder.osuosl.org [140.211.166.138]) by ash.osuosl.org (Postfix) with ESMTP id A27761BFA96 for ; Thu, 30 Apr 2015 18:24:47 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by whitealder.osuosl.org (Postfix) with ESMTP id 9BA45919DE for ; Thu, 30 Apr 2015 18:24:47 +0000 (UTC) X-Virus-Scanned: amavisd-new at osuosl.org Received: from whitealder.osuosl.org ([127.0.0.1]) by localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ao95QdOAspZI for ; Thu, 30 Apr 2015 18:24:46 +0000 (UTC) X-Greylist: delayed 00:05:26 by SQLgrey-1.7.6 Received: from mail-pd0-f169.google.com (mail-pd0-f169.google.com [209.85.192.169]) by whitealder.osuosl.org (Postfix) with ESMTPS id B7A3B91AD9 for ; Thu, 30 Apr 2015 18:24:46 +0000 (UTC) Received: by pdea3 with SMTP id a3so68325544pde.3 for ; Thu, 30 Apr 2015 11:24:46 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xvrTzNgsjE9Gsn17tCxiWvCBxqAAM1NncEaleX+gbHQ=; b=UVrE9N32as41RixuegZLVivOaYx1wqaoJii+CIbaoEhUv+Mj81mQxUf2ZMhv4dfrVg ZqEspYqUiwT4DQzK0c8A6gTF+rHtk1iSlxpqs0MS6jj276tSGu/3l+RM7y8eBCwSeILS +2xCLHkGKaPyURfWvReCg6nhyovCqBZUmmr8xY8jSkeQ2w1Z/6kbrmrzHehmxFnynXb2 dAZiVAJ+45neMJm1XacWGs4pUAyS4Zv3t4RNDnYwm5nLG3dGv70VVX7elREokPS5cGIs azToxtz9KFbntOmsCvWRehf6Lr/hAUwZJAg5i6BqXMIdxOPniWpmpAQS3kM9PU+xRaJh ikXg== X-Gm-Message-State: ALoCoQnhRa+ywurOeAEs++CGJB3CAkeoE51BYVU6hEJoQO17gU+WFlJPcb10s/3uItfu3AHK4lak X-Received: by 10.70.129.133 with SMTP id nw5mr10433971pdb.155.1430417961766; Thu, 30 Apr 2015 11:19:21 -0700 (PDT) Received: from tharvey.gw (68-189-91-139.static.snlo.ca.charter.com. [68.189.91.139]) by mx.google.com with ESMTPSA id bs4sm2821374pdb.21.2015.04.30.11.19.20 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 30 Apr 2015 11:19:21 -0700 (PDT) From: Tim Harvey To: Jeff Kirsher Date: Thu, 30 Apr 2015 11:19:13 -0700 Message-Id: <1430417955-28252-2-git-send-email-tharvey@gateworks.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1430417955-28252-1-git-send-email-tharvey@gateworks.com> References: <1430417955-28252-1-git-send-email-tharvey@gateworks.com> Cc: intel-wired-lan@lists.osuosl.org Subject: [Intel-wired-lan] [PATCH 1/3] net: igb: add i210/i211 support for phy read/write X-BeenThere: intel-wired-lan@lists.osuosl.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: Intel Wired Ethernet Linux Kernel Driver Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-wired-lan-bounces@lists.osuosl.org Sender: "Intel-wired-lan" The i210/i211 uses the MDICNFG register for the phy address instead of the MDIC register. Signed-off-by: Tim Harvey --- drivers/net/ethernet/intel/igb/e1000_phy.c | 71 ++++++++++++++++++++++++++---- 1 file changed, 62 insertions(+), 9 deletions(-) diff --git a/drivers/net/ethernet/intel/igb/e1000_phy.c b/drivers/net/ethernet/intel/igb/e1000_phy.c index c1bb64d..2307ac6 100644 --- a/drivers/net/ethernet/intel/igb/e1000_phy.c +++ b/drivers/net/ethernet/intel/igb/e1000_phy.c @@ -135,7 +135,7 @@ out: s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) { struct e1000_phy_info *phy = &hw->phy; - u32 i, mdic = 0; + u32 i, mdicnfg, mdic = 0; s32 ret_val = 0; if (offset > MAX_PHY_REG_ADDRESS) { @@ -148,11 +148,25 @@ s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) * Control register. The MAC will take care of interfacing with the * PHY to retrieve the desired data. */ - mdic = ((offset << E1000_MDIC_REG_SHIFT) | - (phy->addr << E1000_MDIC_PHY_SHIFT) | - (E1000_MDIC_OP_READ)); + switch (hw->mac.type) { + case e1000_i210: + case e1000_i211: + mdicnfg = rd32(E1000_MDICNFG); + mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); + mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT); + wr32(E1000_MDICNFG, mdicnfg); + mdic = ((offset << E1000_MDIC_REG_SHIFT) | + (E1000_MDIC_OP_READ)); + break; + default: + mdic = ((offset << E1000_MDIC_REG_SHIFT) | + (phy->addr << E1000_MDIC_PHY_SHIFT) | + (E1000_MDIC_OP_READ)); + break; + } wr32(E1000_MDIC, mdic); + wrfl(); /* Poll the ready bit to see if the MDI read completed * Increasing the time out as testing showed failures with @@ -177,6 +191,18 @@ s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) *data = (u16) mdic; out: + switch (hw->mac.type) { + /* restore MDICNFG to have phy's addr */ + case e1000_i210: + case e1000_i211: + mdicnfg = rd32(E1000_MDICNFG); + mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); + mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT); + wr32(E1000_MDICNFG, mdicnfg); + break; + default: + break; + } return ret_val; } @@ -191,7 +217,7 @@ out: s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) { struct e1000_phy_info *phy = &hw->phy; - u32 i, mdic = 0; + u32 i, mdicnfg, mdic = 0; s32 ret_val = 0; if (offset > MAX_PHY_REG_ADDRESS) { @@ -204,12 +230,27 @@ s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) * Control register. The MAC will take care of interfacing with the * PHY to retrieve the desired data. */ - mdic = (((u32)data) | - (offset << E1000_MDIC_REG_SHIFT) | - (phy->addr << E1000_MDIC_PHY_SHIFT) | - (E1000_MDIC_OP_WRITE)); + switch (hw->mac.type) { + case e1000_i210: + case e1000_i211: + mdicnfg = rd32(E1000_MDICNFG); + mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); + mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT); + wr32(E1000_MDICNFG, mdicnfg); + mdic = (((u32)data) | + (offset << E1000_MDIC_REG_SHIFT) | + (E1000_MDIC_OP_WRITE)); + break; + default: + mdic = (((u32)data) | + (offset << E1000_MDIC_REG_SHIFT) | + (phy->addr << E1000_MDIC_PHY_SHIFT) | + (E1000_MDIC_OP_WRITE)); + break; + } wr32(E1000_MDIC, mdic); + wrfl(); /* Poll the ready bit to see if the MDI read completed * Increasing the time out as testing showed failures with @@ -233,6 +274,18 @@ s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) } out: + switch (hw->mac.type) { + /* restore MDICNFG to have phy's addr */ + case e1000_i210: + case e1000_i211: + mdicnfg = rd32(E1000_MDICNFG); + mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); + mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT); + wr32(E1000_MDICNFG, mdicnfg); + break; + default: + break; + } return ret_val; }